Change in coreboot[master]: soc/intel/skylake: add soc implementation for ETR address API
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36569 )
Change subject: soc/intel/skylake: add soc implementation for ETR address API ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36569/9/src/soc/intel/skylake/pmuti... File src/soc/intel/skylake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/36569/9/src/soc/intel/skylake/pmuti... PS9, Line 178: return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR); See request in CB:36686 about placing comments caching these values is forbidden.
I find the shift <<12 here somewhat ugly, but we have a bit of a problem with pci_devfn_t definition anyways to deal with at a later date, so I guess this can be dealt with later.
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Kyösti Mälkki (Code Review)