Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39851 )
Change subject: nb/intel/sandybridge: Refactor get_mem_min_tck ......................................................................
nb/intel/sandybridge: Refactor get_mem_min_tck
It is not necessary to pass its value around various function calls. Move it closer to where it is actually used, so as to make it static. Also, use config_of_soc and flip the branches of the first conditional.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 4 files changed, 79 insertions(+), 74 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/39851/1
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b096a11..1ac9eaf 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -214,7 +214,7 @@ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); }
-static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) +static void init_dram_ddr3(int s3resume, const u32 cpuid) { int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; @@ -301,7 +301,6 @@ if (!fast_boot) { /* Reset internal state */ memset(&ctrl, 0, sizeof(ctrl)); - ctrl.tCK = min_tck;
/* Get architecture */ ctrl.cpu = cpuid; @@ -321,7 +320,6 @@
/* Reset internal state */ memset(&ctrl, 0, sizeof(ctrl)); - ctrl.tCK = min_tck;
/* Get architecture */ ctrl.cpu = cpuid; @@ -374,5 +372,5 @@
timestamp_add_now(TS_BEFORE_INITRAM);
- init_dram_ddr3(get_mem_min_tck(), s3resume, cpu_get_cpuid()); + init_dram_ddr3(s3resume, cpu_get_cpuid()); } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4ba5b59..39938e9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -350,75 +350,6 @@ } }
-#define DEFAULT_TCK TCK_800MHZ - -unsigned int get_mem_min_tck(void) -{ - u32 reg32; - u8 rev; - const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg = NULL; - - dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->max_mem_clock_mhz == 0) { - - if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) - return TCK_1333MHZ; - - rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); - - if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { - /* Read Capabilities A Register DMFC bits */ - reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); - reg32 &= 0x7; - - switch (reg32) { - case 7: return TCK_533MHZ; - case 6: return TCK_666MHZ; - case 5: return TCK_800MHZ; - /* Reserved */ - default: - break; - } - } else { - /* Read Capabilities B Register DMFC bits */ - reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); - reg32 = (reg32 >> 4) & 0x7; - - switch (reg32) { - case 7: return TCK_533MHZ; - case 6: return TCK_666MHZ; - case 5: return TCK_800MHZ; - case 4: return TCK_933MHZ; - case 3: return TCK_1066MHZ; - case 2: return TCK_1200MHZ; - case 1: return TCK_1333MHZ; - /* Reserved */ - default: - break; - } - } - return DEFAULT_TCK; - } else { - if (cfg->max_mem_clock_mhz >= 1066) - return TCK_1066MHZ; - else if (cfg->max_mem_clock_mhz >= 933) - return TCK_933MHZ; - else if (cfg->max_mem_clock_mhz >= 800) - return TCK_800MHZ; - else if (cfg->max_mem_clock_mhz >= 666) - return TCK_666MHZ; - else if (cfg->max_mem_clock_mhz >= 533) - return TCK_533MHZ; - else - return TCK_400MHZ; - } -} - #define DEFAULT_PCI_MMIO_SIZE 2048
static unsigned int get_mmio_size(void) diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index fef4419..a610d45 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -170,7 +170,6 @@ void dram_dimm_mapping(ramctr_timing *ctrl); void dram_dimm_set_mapping(ramctr_timing *ctrl); void dram_zones(ramctr_timing *ctrl, int training); -unsigned int get_mem_min_tck(void); void dram_memorymap(ramctr_timing *ctrl, int me_uma_size); void dram_jedecreset(ramctr_timing *ctrl); int read_training(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 01ff1fa..46310c7 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -4,7 +4,10 @@ #include <console/console.h> #include <console/usb.h> #include <delay.h> +#include <device/device.h> +#include <device/pci_def.h> #include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/chip.h> #include "raminit_native.h" #include "raminit_common.h" #include "raminit_tables.h" @@ -178,6 +181,78 @@ } }
+#define DEFAULT_TCK TCK_800MHZ + +static unsigned int get_mem_min_tck(void) +{ + u32 reg32; + u8 rev; + const struct northbridge_intel_sandybridge_config *cfg = NULL; + + /* Actually, config of MCH or Host Bridge */ + cfg = config_of_soc(); + + /* If non-zero, it was set in the devicetree */ + if (cfg->max_mem_clock_mhz) { + + if (cfg->max_mem_clock_mhz >= 1066) + return TCK_1066MHZ; + + else if (cfg->max_mem_clock_mhz >= 933) + return TCK_933MHZ; + + else if (cfg->max_mem_clock_mhz >= 800) + return TCK_800MHZ; + + else if (cfg->max_mem_clock_mhz >= 666) + return TCK_666MHZ; + + else if (cfg->max_mem_clock_mhz >= 533) + return TCK_533MHZ; + + else + return TCK_400MHZ; + } + + if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) + return TCK_1333MHZ; + + rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); + + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { + /* Read Capabilities A Register DMFC bits */ + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); + reg32 &= 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + /* Reserved */ + default: + break; + } + } else { + /* Read Capabilities B Register DMFC bits */ + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); + reg32 = (reg32 >> 4) & 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + case 4: return TCK_933MHZ; + case 3: return TCK_1066MHZ; + case 2: return TCK_1200MHZ; + case 1: return TCK_1333MHZ; + /* Reserved */ + default: + break; + } + } + return DEFAULT_TCK; +} + static void find_cas_tck(ramctr_timing *ctrl) { u8 val; @@ -192,6 +267,8 @@
printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support);
+ ctrl->tCK = get_mem_min_tck(); + /* Find CAS latency */ while (1) { /*
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39851 )
Change subject: nb/intel/sandybridge: Refactor get_mem_min_tck ......................................................................
Patch Set 5: Code-Review+1
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Matt DeVillier, Paul Menzel, Arthur Heymans, Alexander Couzens, Patrick Rudolph, Felix Held, HAOUAS Elyes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39851
to look at the new patch set (#7).
Change subject: nb/intel/sandybridge: Refactor get_mem_min_tck ......................................................................
nb/intel/sandybridge: Refactor get_mem_min_tck
It is not necessary to pass its value around various function calls. Move it closer to where it is actually used, so as to make it static. Also, use config_of_soc and flip the branches of the first conditional.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 4 files changed, 82 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/39851/7
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39851 )
Change subject: nb/intel/sandybridge: Refactor get_mem_min_tck ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Looks good
https://review.coreboot.org/c/coreboot/+/39851/7/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_native.c:
https://review.coreboot.org/c/coreboot/+/39851/7/src/northbridge/intel/sandy... PS7, Line 194: max_mem_clock_mhz Maybe outside the scope of this patch but why are values higher than 1066MHz not possible via devicetree override but are with Kconfig?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39851 )
Change subject: nb/intel/sandybridge: Refactor get_mem_min_tck ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39851/7/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_native.c:
https://review.coreboot.org/c/coreboot/+/39851/7/src/northbridge/intel/sandy... PS7, Line 194: max_mem_clock_mhz
Maybe outside the scope of this patch but why are values higher than 1066MHz not possible via device […]
That was probably because getting things stable at such high frequencies is quite troublesome. We only recently got 2400 MHz to work fine.
Also, this isn't really doing what it says... It forces a certain frequency, ignoring all the fuses. So, not really "max" memory frequency, but rather "mem_clock_mhz"... This can be taken care of in a subsequent patch.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39851 )
Change subject: nb/intel/sandybridge: Refactor get_mem_min_tck ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39851/7/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_native.c:
https://review.coreboot.org/c/coreboot/+/39851/7/src/northbridge/intel/sandy... PS7, Line 194: max_mem_clock_mhz
That was probably because getting things stable at such high frequencies is quite troublesome. […]
It's ignoring the max set by fuses but is still limited by SPD min tCK? Maybe call the function get_memctrl_min_tck?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39851 )
Change subject: nb/intel/sandybridge: Refactor get_mem_min_tck ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39851/7/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_native.c:
https://review.coreboot.org/c/coreboot/+/39851/7/src/northbridge/intel/sandy... PS7, Line 194: max_mem_clock_mhz
It's ignoring the max set by fuses but is still limited by SPD min tCK? Maybe call the function get_ […]
I think it's ignoring the memory frequency as well, so it can end up overclocking DIMMs if the CAS latencies provide enough margin... It's a very messy control flow.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39851 )
Change subject: nb/intel/sandybridge: Refactor get_mem_min_tck ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39851/7/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_native.c:
https://review.coreboot.org/c/coreboot/+/39851/7/src/northbridge/intel/sandy... PS7, Line 194: max_mem_clock_mhz
I think it's ignoring the memory frequency as well, so it can end up overclocking DIMMs if the CAS latencies provide enough margin... It's a very messy control flow.
No it looks like finding a proper tCK is still based supported nCAS and tAA which are always fetched from SPD's. This setting is a limit to that computation. I agree that at this stage it is somewhat messy probably because those things were spread across multiple files/functions.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39851 )
Change subject: nb/intel/sandybridge: Refactor get_mem_min_tck ......................................................................
nb/intel/sandybridge: Refactor get_mem_min_tck
It is not necessary to pass its value around various function calls. Move it closer to where it is actually used, so as to make it static. Also, use config_of_soc and flip the branches of the first conditional.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39851 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 4 files changed, 82 insertions(+), 76 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index e138756..6c8145d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -226,11 +226,10 @@ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); }
-static void reinit_ctrl(ramctr_timing *ctrl, int min_tck, const u32 cpuid) +static void reinit_ctrl(ramctr_timing *ctrl, const u32 cpuid) { /* Reset internal state */ memset(ctrl, 0, sizeof(*ctrl)); - ctrl->tCK = min_tck;
/* Get architecture */ ctrl->cpu = cpuid; @@ -243,7 +242,7 @@ ctrl->ecc_forced ? "yes" : "no"); }
-static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) +static void init_dram_ddr3(int s3resume, const u32 cpuid) { int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; @@ -329,7 +328,7 @@ } if (!fast_boot) { /* Reset internal state */ - reinit_ctrl(&ctrl, min_tck, cpuid); + reinit_ctrl(&ctrl, cpuid);
printk(BIOS_INFO, "ECC RAM %s.\n", ctrl.ecc_forced ? "required" : ctrl.ecc_supported ? "supported" : "unsupported"); @@ -348,7 +347,7 @@ printram("Disable failing channel.\n");
/* Reset internal state */ - reinit_ctrl(&ctrl, min_tck, cpuid); + reinit_ctrl(&ctrl, cpuid);
/* Reset DDR3 frequency */ dram_find_spds_ddr3(spds, &ctrl); @@ -398,5 +397,5 @@
timestamp_add_now(TS_BEFORE_INITRAM);
- init_dram_ddr3(get_mem_min_tck(), s3resume, cpu_get_cpuid()); + init_dram_ddr3(s3resume, cpu_get_cpuid()); } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 51f3362..087ba2b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -358,75 +358,6 @@ } }
-#define DEFAULT_TCK TCK_800MHZ - -unsigned int get_mem_min_tck(void) -{ - u32 reg32; - u8 rev; - const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg = NULL; - - dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->max_mem_clock_mhz == 0) { - - if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) - return TCK_1333MHZ; - - rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); - - if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { - /* Read Capabilities A Register DMFC bits */ - reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); - reg32 &= 0x7; - - switch (reg32) { - case 7: return TCK_533MHZ; - case 6: return TCK_666MHZ; - case 5: return TCK_800MHZ; - /* Reserved */ - default: - break; - } - } else { - /* Read Capabilities B Register DMFC bits */ - reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); - reg32 = (reg32 >> 4) & 0x7; - - switch (reg32) { - case 7: return TCK_533MHZ; - case 6: return TCK_666MHZ; - case 5: return TCK_800MHZ; - case 4: return TCK_933MHZ; - case 3: return TCK_1066MHZ; - case 2: return TCK_1200MHZ; - case 1: return TCK_1333MHZ; - /* Reserved */ - default: - break; - } - } - return DEFAULT_TCK; - } else { - if (cfg->max_mem_clock_mhz >= 1066) - return TCK_1066MHZ; - else if (cfg->max_mem_clock_mhz >= 933) - return TCK_933MHZ; - else if (cfg->max_mem_clock_mhz >= 800) - return TCK_800MHZ; - else if (cfg->max_mem_clock_mhz >= 666) - return TCK_666MHZ; - else if (cfg->max_mem_clock_mhz >= 533) - return TCK_533MHZ; - else - return TCK_400MHZ; - } -} - #define DEFAULT_PCI_MMIO_SIZE 2048
static unsigned int get_mmio_size(void) diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 93541b5..314c67d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -174,7 +174,6 @@ void dram_dimm_mapping(ramctr_timing *ctrl); void dram_dimm_set_mapping(ramctr_timing *ctrl, int training); void dram_zones(ramctr_timing *ctrl, int training); -unsigned int get_mem_min_tck(void); void dram_memorymap(ramctr_timing *ctrl, int me_uma_size); void dram_jedecreset(ramctr_timing *ctrl); int read_training(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 99c1a4c..832391f 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -5,7 +5,10 @@ #include <console/console.h> #include <console/usb.h> #include <delay.h> +#include <device/device.h> +#include <device/pci_def.h> #include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/chip.h> #include "raminit_native.h" #include "raminit_common.h" #include "raminit_tables.h" @@ -174,6 +177,78 @@ } }
+#define DEFAULT_TCK TCK_800MHZ + +static unsigned int get_mem_min_tck(void) +{ + u32 reg32; + u8 rev; + const struct northbridge_intel_sandybridge_config *cfg = NULL; + + /* Actually, config of MCH or Host Bridge */ + cfg = config_of_soc(); + + /* If non-zero, it was set in the devicetree */ + if (cfg->max_mem_clock_mhz) { + + if (cfg->max_mem_clock_mhz >= 1066) + return TCK_1066MHZ; + + else if (cfg->max_mem_clock_mhz >= 933) + return TCK_933MHZ; + + else if (cfg->max_mem_clock_mhz >= 800) + return TCK_800MHZ; + + else if (cfg->max_mem_clock_mhz >= 666) + return TCK_666MHZ; + + else if (cfg->max_mem_clock_mhz >= 533) + return TCK_533MHZ; + + else + return TCK_400MHZ; + } + + if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) + return TCK_1333MHZ; + + rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); + + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { + /* Read Capabilities A Register DMFC bits */ + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); + reg32 &= 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + /* Reserved */ + default: + break; + } + } else { + /* Read Capabilities B Register DMFC bits */ + reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); + reg32 = (reg32 >> 4) & 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + case 4: return TCK_933MHZ; + case 3: return TCK_1066MHZ; + case 2: return TCK_1200MHZ; + case 1: return TCK_1333MHZ; + /* Reserved */ + default: + break; + } + } + return DEFAULT_TCK; +} + static void find_cas_tck(ramctr_timing *ctrl) { u8 val; @@ -188,6 +263,8 @@
printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support);
+ ctrl->tCK = get_mem_min_tck(); + /* Find CAS latency */ while (1) { /*
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39851 )
Change subject: nb/intel/sandybridge: Refactor get_mem_min_tck ......................................................................
Patch Set 8:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2469 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2468 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2467 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2466
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
Arthur Heymans (Code Review)
-
Paul Menzel (Code Review)