Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table

[Jianjun Wang (Code Review)]

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu.
Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )

Change subject: coreboot tables: Add PCIe info to coreboot table
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Patch Set 12:

(2 comments)

File src/commonlib/include/commonlib/coreboot_tables.h:

https://review.coreboot.org/c/coreboot/+/63251/comment/6bcfe0e9_01301292 
PS12, Line 151: lb_uint64_t ctrl_base;
> Sorry for my ignorance but what is this exactly? I know PCIe ECAM.

This is the base address for those PCIe controllers that do not support ECAM.
For MediaTek's PCIe controller, we need to setting some registers of PCIe hardware to send the TLP, so pass its base address for payloads to access these registers.

File src/lib/coreboot_table.c:

https://review.coreboot.org/c/coreboot/+/63251/comment/e7eca6c3_93a327df 
PS12, Line 36: __weak enum cb_err lb_fill_pcie(struct lb_pcie *pcie)
             : {
             : 	return CB_ERR;
             : }
> Does it make sense to have a better default? CONFIG_ECAM_MMCONF_BASE_ADDRESS is typically known at b […]

I think we can get the information from device tree directly by define this function, so we don't need to define another macro with same value.