[S] Change in coreboot[main]: sb/intel/bd82x6x/early_usb: Add USB TX/RX gains

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78829?usp=email )

Change subject: sb/intel/bd82x6x/early_usb: Add USB TX/RX gains
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sb/intel/bd82x6x/early_usb: Add USB TX/RX gains

Describe the USB 'current' settings based on MRC.bin that converts
the USB trace length to a predefined register value.
MRC.bin decides which setting to use based on the PC type, mobile
or desktop, and the trace length.

Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/early_usb.c
M src/southbridge/intel/bd82x6x/pch.h
2 files changed, 15 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/78829/1

diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index 27a9c57..1d574e1 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -15,9 +15,9 @@
    	/* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
    	/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
    };
-	const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51,
-				 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357,
-				 0x20000353 };
+	const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT,
+				 USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f,
+				 USBIR_TXRX_GAIN_DESKTOP_LOW, 0x20000357, 0x20000353 };
    int i;

/* Unlock registers.  */
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 6d164ea..656b641 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -380,6 +380,18 @@
 #define USBIR12		0x3530	/* 32bit */
 #define USBIR13		0x3534	/* 32bit */

+/* Up to 5" onboard trace length */
+#define USBIR_TXRX_GAIN_MOBILE_LOW	0x20000153
+
+/* Up to 6" onboard trace length */
+#define USBIR_TXRX_GAIN_DESKTOP_LOW	0x20000F53
+
+/* Up to 14" onboard trace length, up to 8" on wires */
+#define USBIR_TXRX_GAIN_DEFAULT		0x20000f57
+
+/* Up to 10" onboard trace length, up to 15" on wires */
+#define USBIR_TXRX_GAIN_HIGH		0x2000055B
+
 /* Miscellaneous Control Register */
 #define MISCCTL		0x3590	/* 32bit */
 /* USB Port Disable Override */