Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock

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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 )

Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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Patch Set 8:

(1 comment)

https://review.coreboot.org/#/c/25442/8/src/soc/intel/denverton_ns/lpc.c 
File src/soc/intel/denverton_ns/lpc.c:

https://review.coreboot.org/#/c/25442/8/src/soc/intel/denverton_ns/lpc.c@418 
PS8, Line 418: 	if(!relax_security)
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