Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Configure IO APIC

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29423

Change subject: src/soc/intel/braswell/southcluster.c: Configure IO APIC
......................................................................

src/soc/intel/braswell/southcluster.c: Configure IO APIC

IO APIC is not configured.
Add sc_enable_ioapic().

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/southcluster.c
1 file changed, 55 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29423/1

diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index ca87d63..16ef09a 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -18,6 +18,7 @@
 #include <arch/io.h>
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
+#include <arch/ioapic.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include "chip.h"
@@ -72,6 +73,9 @@
    add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
    add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
    add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
+	add_mmio_resource(dev, 0xfff, 0xffffffff - CONFIG_CBFS_SIZE + 1,
+			CONFIG_CBFS_SIZE);	/* BIOS ROM */
+	add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */
 }

/* Default IO range claimed by the LPC device. The upper bound is exclusive. */
@@ -93,6 +97,49 @@
    return 0;
 }

+static void sc_enable_ioapic(struct device *dev)
+{
+	int i;
+	u32 reg32;
+	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+	u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f);
+
+	/*
+	 * Enable ACPI I/O and power management.
+	 * Set SCI IRQ to IRQ9
+	 */
+	write32(ilb_base + ILB_OIC, 0x100);  /* AEN */
+	reg32 = read32(ilb_base + ILB_OIC);  /* Read back per BWG */
+	write32(ilb_base + ILB_ACTL, 0);  /* ACTL bit 2:0 SCIS IRQ9 */
+
+	*ioapic_index = 0;
+	*ioapic_data = (1 << 25);
+
+	/* affirm full set of redirection table entries ("write once") */
+	*ioapic_index = 1;
+	reg32 = *ioapic_data;
+	*ioapic_index = 1;
+	*ioapic_data = reg32;
+
+	*ioapic_index = 0;
+	reg32 = *ioapic_data;
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+	if (reg32 != (1 << 25))
+		die("APIC Error\n");
+
+	printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
+	for (i=0; i<3; i++) {
+		*ioapic_index = i;
+		printk(BIOS_SPEW, "  reg 0x%04x:", i);
+		reg32 = *ioapic_data;
+		printk(BIOS_SPEW, " 0x%08x\n", reg32);
+	}
+
+	*ioapic_index = 3; /* Select Boot Configuration register. */
+	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+}
+
 /*
  * Note: this function assumes there is no overlap with the default LPC device's
  * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
@@ -168,6 +215,14 @@
    printk(BIOS_SPEW, "%s/%s (%s)\n",
    		__FILE__, __func__, dev_name(dev));

+	/* Set the value for PCI command register. */
+	pci_write_config16(dev, PCI_COMMAND,
+		PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+		PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
+
+	/* IO APIC initialization. */
+	sc_enable_ioapic(dev);
+
    /* Set up the PIRQ PIC routing based on static config. */
    for (i = 0; i < NUM_PIRQS; i++)
    	write8((void *)(pr_base + i*sizeof(ir->pic[i])),