[L] Change in coreboot[main]: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)

[Federico Amedeo Izzo (Code Review)]

Attention is currently required from: Angel Pons, Felix Held, Felix Singer, Paul Menzel.

Federico Amedeo Izzo has posted comments on this change by Federico Amedeo Izzo. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email )

Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
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Patch Set 15:

(3 comments)

Patchset:

PS15: 
I managed to generate a `gpio.h` using high level macros as suggested by @[e-mail], now the code looks much cleaner.

There are no more open points on my side.
I'm running this port on my home NAS and I'm happy with it 😊.

File src/mainboard/aoostar/wtr_r1/gpio.h:

PS14:
> i wonder if the more high level gpio configuration macros could be used here instead of _PAD_CFG_STR […]

Thank you for the heads up! I figured out running `intelp2m` with `-n` does exactly that.
I tested the result and got no regressions.

File src/mainboard/aoostar/wtr_r1/gpio.h:

https://review.coreboot.org/c/coreboot/+/82010/comment/55954dde_cdda1306?usp... :
PS10, Line 14: _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) |
             : 			PAD_BUF(TX_RX_DISABLE),	PAD_IOSSTATE(IGNORE)),	/* CORE_VID0 */
> Would be great if these could be translated to more readable macros, like […]

I solved this, see comment by @[e-mail]