Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: [WIP] soc/amd/cezanne: add GPIO definitions ......................................................................
[WIP] soc/amd/cezanne: add GPIO definitions
TODO: needs verification
Change-Id: I67930267a89ba0c64ec7e40e2bfa30a0618d104b Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A src/soc/amd/cezanne/include/soc/gpio.h 1 file changed, 279 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48564/1
diff --git a/src/soc/amd/cezanne/include/soc/gpio.h b/src/soc/amd/cezanne/include/soc/gpio.h new file mode 100644 index 0000000..4aa901a --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/gpio.h @@ -0,0 +1,279 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_PICASSO_GPIO_H +#define AMD_PICASSO_GPIO_H + +#define GPIO_DEVICE_NAME "AMD0030" +#define GPIO_DEVICE_DESC "GPIO Controller" + +#ifndef __ACPI__ +#include <soc/iomap.h> +#include <amdblocks/gpio_banks.h> + +/* The following sections describe only the GPIOs defined for this SOC */ + +#define SOC_GPIO_TOTAL_PINS 149 + +/* Bank 0: GPIO_0 - GPIO_63 */ +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_26 26 +#define GPIO_27 27 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 +#define GPIO_40 40 +#define GPIO_42 42 + +/* Bank 1: GPIO_64 - GPIO_127 */ +#define GPIO_67 67 +#define GPIO_68 68 +#define GPIO_69 69 +#define GPIO_70 70 +#define GPIO_74 74 +#define GPIO_75 75 +#define GPIO_76 76 +#define GPIO_84 84 +#define GPIO_85 85 +#define GPIO_86 86 +#define GPIO_87 87 +#define GPIO_88 88 +#define GPIO_89 89 +#define GPIO_90 90 +#define GPIO_91 91 +#define GPIO_92 92 +#define GPIO_104 104 +#define GPIO_105 105 +#define GPIO_106 106 +#define GPIO_107 107 +#define GPIO_108 108 +#define GPIO_109 109 +#define GPIO_113 113 +#define GPIO_114 114 +#define GPIO_115 115 +#define GPIO_116 116 +#define GPIO_120 120 +#define GPIO_121 121 + +/* Bank 2: GPIO_128 - GPIO_191 */ +#define GPIO_129 129 +#define GPIO_130 130 +#define GPIO_131 131 +#define GPIO_132 132 +#define GPIO_140 140 +#define GPIO_141 141 +#define GPIO_142 142 +#define GPIO_143 143 +#define GPIO_144 144 +#define GPIO_145 145 +#define GPIO_146 146 +#define GPIO_147 147 +#define GPIO_148 148 + +/* IOMUX function names and values generated from PPR. */ +#define GPIO_0_IOMUX_PWR_BTN_L 0 +#define GPIO_0_IOMUX_GPIOxx 1 +#define GPIO_1_IOMUX_SYS_RESET_L 0 +#define GPIO_1_IOMUX_GPIOxx 1 +#define GPIO_2_IOMUX_WAKE_L 0 +#define GPIO_2_IOMUX_GPIOxx 1 +#define GPIO_3_IOMUX_GPIOxx 0 +#define GPIO_4_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_DEVSLP0 1 +#define GPIO_5_IOMUX_DEVSLP2 2 +#define GPIO_6_IOMUX_GPIOxx 0 +#define GPIO_6_IOMUX_DEVSLP1 1 +#define GPIO_6_IOMUX_DEVSLP3 2 +#define GPIO_7_IOMUX_GPIOxx 0 +#define GPIO_7_IOMUX_ACP_I2S_SDIN 1 +#define GPIO_8_IOMUX_GPIOxx 0 +#define GPIO_8_IOMUX_ACP_I2S_LRCLK 1 +#define GPIO_9_IOMUX_GPIOxx 0 +#define GPIO_9_IOMUX_MDIO1_SCL 2 +#define GPIO_10_IOMUX_GPIOxx 0 +#define GPIO_10_IOMUX_S0A3 1 +#define GPIO_10_IOMUX_MDIO0_SCL 3 +#define GPIO_11_IOMUX_GPIOxx 0 +#define GPIO_11_IOMUX_BLINK 1 +#define GPIO_12_IOMUX_LLB_L 0 +#define GPIO_12_IOMUX_GPIOxx 1 +#define GPIO_16_IOMUX_USB_OC0_L 0 +#define GPIO_16_IOMUX_GPIOxx 1 +#define GPIO_17_IOMUX_USB_OC1_L 0 +#define GPIO_17_IOMUX_GPIOxx 1 +#define GPIO_18_IOMUX_USB_OC2_L 0 +#define GPIO_18_IOMUX_GPIOxx 1 +#define GPIO_19_IOMUX_SCL1 0 +#define GPIO_19_IOMUX_I2C3_SCL 1 +#define GPIO_19_IOMUX_GPIOxx 2 +#define GPIO_20_IOMUX_SDA1 0 +#define GPIO_20_IOMUX_I2C3_SDA 1 +#define GPIO_20_IOMUX_GPIOxx 2 +#define GPIO_21_IOMUX_LPC_PD_L 0 +#define GPIO_21_IOMUX_EMMC_CMD 1 +#define GPIO_21_IOMUX_GPIOxx 2 +#define GPIO_22_IOMUX_LPC_PME_L 0 +#define GPIO_22_IOMUX_EMMC_PWR_CTRL 1 +#define GPIO_22_IOMUX_GPIOxx 2 +#define GPIO_23_IOMUX_AC_PRES 0 +#define GPIO_23_IOMUX_MDIO1_SDA 2 +#define GPIO_23_IOMUX_GPIOxx 3 +#define GPIO_24_IOMUX_USB_OC3_L 0 +#define GPIO_24_IOMUX_GPIOxx 1 +#define GPIO_26_IOMUX_PCIE_RST_L 0 +#define GPIO_26_IOMUX_GPIOxx 1 +#define GPIO_27_IOMUX_GPIOxx 0 +#define GPIO_27_IOMUX_PCIE_RST1_L 1 +#define GPIO_29_IOMUX_SPI_TPM_CS_L 0 +#define GPIO_29_IOMUX_GPIOxx 1 +#define GPIO_30_IOMUX_SPI_CS2_L 0 +#define GPIO_30_IOMUX_ESPI_CS_L 1 +#define GPIO_30_IOMUX_GPIOxx 2 +#define GPIO_31_IOMUX_SPI_CS3_L 0 +#define GPIO_31_IOMUX_ESPI_CS_L 1 +#define GPIO_31_IOMUX_GPIOxx 2 +#define GPIO_32_IOMUX_LPC_RST_L 0 +#define GPIO_32_IOMUX_SD_WP_L 1 +#define GPIO_32_IOMUX_GPIOxx 2 +#define GPIO_40_IOMUX_GPIOxx 0 +#define GPIO_40_IOMUX_MDIO0_SDA 2 +#define GPIO_42_IOMUX_GPIOxx 0 +#define GPIO_67_IOMUX_SPI_ROM_REQ 0 +#define GPIO_67_IOMUX_GPIOxx 1 +#define GPIO_68_IOMUX_GPIOxx 0 +#define GPIO_68_IOMUX_EMMC_CD 1 +#define GPIO_69_IOMUX_GPIOxx 0 +#define GPIO_70_IOMUX_GPIOxx 0 +#define GPIO_70_IOMUX_EMMC_CLK 1 +#define GPIO_70_IOMUX_SD_CLK 2 +#define GPIO_74_IOMUX_LPCCLK0 0 +#define GPIO_74_IOMUX_EMMC_DATA4 1 +#define GPIO_74_IOMUX_GPIOxx 2 +#define GPIO_75_IOMUX_LPCCLK1 0 +#define GPIO_75_IOMUX_EMMC_DATA6 1 +#define GPIO_75_IOMUX_GPIOxx 2 +#define GPIO_76_IOMUX_SPI_ROM_GNT 0 +#define GPIO_76_IOMUX_GPIOxx 1 +#define GPIO_84_IOMUX_FANIN0 0 +#define GPIO_84_IOMUX_GPIOxx 1 +#define GPIO_85_IOMUX_FANOUT0 0 +#define GPIO_85_IOMUX_GPIOxx 1 +#define GPIO_86_IOMUX_LPC_SMI_L 0 +#define GPIO_86_IOMUX_GPIOxx 1 +#define GPIO_86_IOMUX_SPI_CLK 2 +#define GPIO_87_IOMUX_SERIRQ 0 +#define GPIO_87_IOMUX_EMMC_DATA7 1 +#define GPIO_87_IOMUX_GPIOxx 2 +#define GPIO_88_IOMUX_LPC_CLKRUN_L 0 +#define GPIO_88_IOMUX_EMMC_DATA5 1 +#define GPIO_88_IOMUX_GPIOxx 2 +#define GPIO_89_IOMUX_GENINT1_L 0 +#define GPIO_89_IOMUX_PSP_INTR0 1 +#define GPIO_89_IOMUX_GPIOxx 2 +#define GPIO_90_IOMUX_GENINT2_L 0 +#define GPIO_90_IOMUX_PSP_INTR1 1 +#define GPIO_90_IOMUX_GPIOxx 2 +#define GPIO_91_IOMUX_SPKR 0 +#define GPIO_91_IOMUX_GPIOxx 1 +#define GPIO_92_IOMUX_CLK_REQ0_L 0 +#define GPIO_92_IOMUX_SATA_IS0_L 1 +#define GPIO_92_IOMUX_SATA_ZP0_L 2 +#define GPIO_92_IOMUX_GPIOxx 3 +#define GPIO_104_IOMUX_LAD0 0 +#define GPIO_104_IOMUX_SPI2_DO_ESPI2_D0 1 +#define GPIO_104_IOMUX_SD0_DATA0 2 +#define GPIO_104_IOMUX_GPIOxx 3 +#define GPIO_105_IOMUX_LAD1 0 +#define GPIO_105_IOMUX_SPI2_DI_ESPI2_D1 1 +#define GPIO_105_IOMUX_SD0_DATA1 2 +#define GPIO_105_IOMUX_GPIOxx 3 +#define GPIO_106_IOMUX_LAD2 0 +#define GPIO_106_IOMUX_EMMC_SPI2_WP_L_ESPI2_D2 1 +#define GPIO_106_IOMUX_EMMC_SD0_DATA2 2 +#define GPIO_106_IOMUX_GPIOxx 3 +#define GPIO_107_IOMUX_LAD3 0 +#define GPIO_107_IOMUX_SPI2_HOLD_L_ESPI2_D3 1 +#define GPIO_107_IOMUX_SD0_DATA3 2 +#define GPIO_107_IOMUX_GPIOxx 3 +#define GPIO_108_IOMUX_LDRQ0_L 0 +#define GPIO_108_IOMUX_ESPI_ALERT_D1 1 +#define GPIO_108_IOMUX_GPIOxx 2 +#define GPIO_109_IOMUX_LFRAME_L 0 +#define GPIO_109_IOMUX_EMMC_DS 1 +#define GPIO_109_IOMUX_GPIOxx 2 +#define GPIO_113_IOMUX_SCL0 0 +#define GPIO_113_IOMUX_I2C2_SCL 1 +#define GPIO_113_IOMUX_GPIOxx 2 +#define GPIO_114_IOMUX_SDA0 0 +#define GPIO_114_IOMUX_I2C2_SDA 1 +#define GPIO_114_IOMUX_GPIOxx 2 +#define GPIO_115_IOMUX_CLK_REQ1_L 0 +#define GPIO_115_IOMUX_GPIOxx 1 +#define GPIO_116_IOMUX_CLK_REQ2_L 0 +#define GPIO_116_IOMUX_GPIOxx 1 +#define GPIO_120_IOMUX_CLK_REQ5_L 0 +#define GPIO_120_IOMUX_GPIOxx 1 +#define GPIO_121_IOMUX_CLK_REQ6_L 0 +#define GPIO_121_IOMUX_GPIOxx 1 +#define GPIO_129_IOMUX_KBRST_L 0 +#define GPIO_129_IOMUX_GPIOxx 2 +#define GPIO_130_IOMUX_SATA_ACT_L 0 +#define GPIO_130_IOMUX_GPIOxx 1 +#define GPIO_131_IOMUX_CLK_REQ3_L 0 +#define GPIO_131_IOMUX_SATA_IS1_L 1 +#define GPIO_131_IOMUX_SATA_ZP1_L 2 +#define GPIO_131_IOMUX_GPIOxx 3 +#define GPIO_132_IOMUX_CLK_REQ4_L 0 +#define GPIO_132_IOMUX_OSCIN 1 +#define GPIO_132_IOMUX_GPIOxx 2 +#define GPIO_140_IOMUX_GPIOxx 0 +#define GPIO_140_IOMUX_UART0_CTS_L 1 +#define GPIO_140_IOMUX_UART1_TXD 2 +#define GPIO_140_IOMUX_SD0_DATA1 3 +#define GPIO_141_IOMUX_GPIOxx 0 +#define GPIO_141_IOMUX_UART0_RXD 1 +#define GPIO_141_IOMUX_SD0_DATA3 2 +#define GPIO_142_IOMUX_GPIOxx 0 +#define GPIO_142_IOMUX_UART0_RTS_L 1 +#define GPIO_142_IOMUX_UART1_RXD 2 +#define GPIO_142_IOMUX_SD0_DATA0 3 +#define GPIO_143_IOMUX_GPIOxx 0 +#define GPIO_143_IOMUX_UART0_TXD 1 +#define GPIO_143_IOMUX_SD0_DATA2 2 +#define GPIO_144_IOMUX_GPIOxx 0 +#define GPIO_144_IOMUX_UART0_INTR 2 +#define GPIO_145_IOMUX_I2C0_SCL 0 +#define GPIO_145_IOMUX_GPIOxx 1 +#define GPIO_146_IOMUX_I2C0_SDA 0 +#define GPIO_146_IOMUX_GPIOxx 1 +#define GPIO_147_IOMUX_I2C1_SCL 0 +#define GPIO_147_IOMUX_GPIOxx 1 +#define GPIO_148_IOMUX_I2C1_SDA 0 +#define GPIO_148_IOMUX_GPIOxx 1 + +#define GPIO_2_EVENT GEVENT_8 + +#endif /* __ACPI__ */ +#endif /* AMD_PICASSO_GPIO_H */
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: [WIP] soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 1:
I looked at the CZN PPR when I did this, but it should also be checked against the RN PPR
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: [WIP] soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 140: #define GPIO_23_IOMUX_AC_PRES 0 'PRES' may be misspelled - perhaps 'PRESS'?
Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: [WIP] soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 1:
(5 comments)
For the GPIO14x different between RN and CZN, I really doubt there is something wrong with the PPR.
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 138: #define GPIO_22_IOMUX_EMMC_PWR_CTRL 1 #define GPIO_22_IOMUX_EMMC_PRW_CTRL 1 Is this PRW in Picasso folder a typo?
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 251: #define GPIO_140_IOMUX_GPIOxx 0 : #define GPIO_140_IOMUX_UART0_CTS_L 1 GPIO is func 1, and UART0_CTS_L is func 0, in RN PPR.
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 255: #define GPIO_141_IOMUX_GPIOxx 0 : #define GPIO_141_IOMUX_UART0_RXD 1 For RN, same as 140.
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 258: #define GPIO_142_IOMUX_GPIOxx 0 : #define GPIO_142_IOMUX_UART0_RTS_L 1 : #define GPIO_142_IOMUX_UART1_RXD 2 : #define GPIO_142_IOMUX_SD0_DATA0 3 For RN, For 142, GPIO is func 2. And func 0,1 are not right either.
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 265: #define GPIO_144_IOMUX_GPIOxx 0 : #define GPIO_144_IOMUX_UART0_INTR 2 For RN, switch.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: [WIP] soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 138: #define GPIO_22_IOMUX_EMMC_PWR_CTRL 1
#define GPIO_22_IOMUX_EMMC_PRW_CTRL 1 […]
i'd assume that it's a typo in the picasso herader; see also the Mandolin schematics where it's emmc pwr ctrl
Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: [WIP] soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 138: #define GPIO_22_IOMUX_EMMC_PWR_CTRL 1
i'd assume that it's a typo in the picasso herader; see also the Mandolin schematics where it's emmc […]
Done. New change has been uploaded. https://review.coreboot.org/c/coreboot/+/48633
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: [WIP] soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 251: #define GPIO_140_IOMUX_GPIOxx 0 : #define GPIO_140_IOMUX_UART0_CTS_L 1
GPIO is func 1, and UART0_CTS_L is func 0, in RN PPR.
I just had a look at the revision 3.06 of the Renoir PPR and it matches both revision 3.00 of the Cezanne PPR and the code here. same for the other 3 ones below
Hello Bao Zheng, build bot (Jenkins), Jason Glenesk, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48564
to look at the new patch set (#2).
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
soc/amd/cezanne: add GPIO definitions
Change-Id: I67930267a89ba0c64ec7e40e2bfa30a0618d104b Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A src/soc/amd/cezanne/include/soc/gpio.h 1 file changed, 279 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48564/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... PS2, Line 140: #define GPIO_23_IOMUX_AC_PRES 0 'PRES' may be misspelled - perhaps 'PRESS'?
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 2:
(6 comments)
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... PS2, Line 3: AMD_PICASSO_GPIO_H change name
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... PS2, Line 116: #define GPIO_10_IOMUX_S0A3 1 nit, it looks like 2 is missing. PPR calls it reserved. could consider a comment for "reserved".
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... PS2, Line 140: #define GPIO_23_IOMUX_AC_PRES 0
'PRES' may be misspelled - perhaps 'PRESS'?
Same re. comment of reserved value 21
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... PS2, Line 161: #define same comment
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... PS2, Line 241: define Same comment
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... PS2, Line 266: IOMUX_UART0_INTR 2 same comment
Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 251: #define GPIO_140_IOMUX_GPIOxx 0 : #define GPIO_140_IOMUX_UART0_CTS_L 1
I just had a look at the revision 3.06 of the Renoir PPR and it matches both revision 3. […]
Done. Yes. I downloaded the 3.06 and found some GPIO definitions has changed.
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 255: #define GPIO_141_IOMUX_GPIOxx 0 : #define GPIO_141_IOMUX_UART0_RXD 1
For RN, same as 140.
Done
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 258: #define GPIO_142_IOMUX_GPIOxx 0 : #define GPIO_142_IOMUX_UART0_RTS_L 1 : #define GPIO_142_IOMUX_UART1_RXD 2 : #define GPIO_142_IOMUX_SD0_DATA0 3
For RN, […]
Done
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 265: #define GPIO_144_IOMUX_GPIOxx 0 : #define GPIO_144_IOMUX_UART0_INTR 2
For RN, switch.
Done
Hello Bao Zheng, build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48564
to look at the new patch set (#3).
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
soc/amd/cezanne: add GPIO definitions
Change-Id: I67930267a89ba0c64ec7e40e2bfa30a0618d104b Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A src/soc/amd/cezanne/include/soc/gpio.h 1 file changed, 285 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48564/3
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... PS2, Line 3: AMD_PICASSO_GPIO_H
change name
Done
https://review.coreboot.org/c/coreboot/+/48564/2/src/soc/amd/cezanne/include... PS2, Line 116: #define GPIO_10_IOMUX_S0A3 1
nit, it looks like 2 is missing. PPR calls it reserved. could consider a comment for "reserved".
done for all comments and one more
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... PS3, Line 142: #define GPIO_23_IOMUX_AC_PRES 0 'PRES' may be misspelled - perhaps 'PRESS'?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... PS3, Line 7: GPIO_DEVICE_DESC nit: Is there any advantage of having a macro for this? It is used in just one place in the ACPI node for GPIO controller. GPIO_DEVICE_NAME gets used by other code as well, so that seems fine.
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... PS3, Line 282: GPIO_2_EVENT Why a special macro for GPIO_2 event?
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... PS3, Line 95: GPIO_0_IOMUX_PWR_BTN_L Did you generate the list?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... PS3, Line 7: GPIO_DEVICE_DESC
nit: Is there any advantage of having a macro for this? It is used in just one place in the ACPI nod […]
i can look into refactoring this later, but for now, i try to stay close to what's done in picasso to make the refactoring easier
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... PS3, Line 95: GPIO_0_IOMUX_PWR_BTN_L
Did you generate the list?
it started as copy of the file from picasso, but got adapter for cezanne/renoir. should i remove the comment above?
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... PS3, Line 282: GPIO_2_EVENT
Why a special macro for GPIO_2 event?
that one is currently used in the soc's gpio.c file and will be removed in a future common refactoring. currently my priority is getting bootblock and enough of ramstage working to unblock testing for the fsp development
Hello build bot (Jenkins), Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48564
to look at the new patch set (#4).
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
soc/amd/cezanne: add GPIO definitions
Change-Id: I67930267a89ba0c64ec7e40e2bfa30a0618d104b Signed-off-by: Felix Held felix-coreboot@felixheld.de --- A src/soc/amd/cezanne/include/soc/gpio.h 1 file changed, 285 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48564/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... PS4, Line 142: #define GPIO_23_IOMUX_AC_PRES 0 'PRES' may be misspelled - perhaps 'PRESS'?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/3/src/soc/amd/cezanne/include... PS3, Line 95: GPIO_0_IOMUX_PWR_BTN_L
it started as copy of the file from picasso, but got adapter for cezanne/renoir. […]
Done
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 4: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... PS4, Line 48: I see 43-62 in the PPR. Do we want these?
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... PS4, Line 93: 172-183?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... PS4, Line 48:
I see 43-62 in the PPR. […]
oh, those aren't in the IOMUX table and are also missing in picasso. since those don't have an associated IOMUX register, i'm not sure how to handle those properly. it'll probably work if i add #define GPIO_x_IOMUX_GPIOxx 0 for each of those, but i'm not 100% confident about that. so i'd suggest to keep it as it is right now and add those if we need them later on
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... PS4, Line 93:
172-183?
same situation as with the ones i commented about above
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 4: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... PS4, Line 48:
oh, those aren't in the IOMUX table and are also missing in picasso. […]
Sounds good. Can you file a bug so we don't lose track of the work. We might need to refactor some of the gpio code to handle these cases.
https://review.coreboot.org/c/coreboot/+/48564/4/src/soc/amd/cezanne/include... PS4, Line 93:
same situation as with the ones i commented about above
Ack
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: soc/amd/cezanne: add GPIO definitions ......................................................................
soc/amd/cezanne: add GPIO definitions
Change-Id: I67930267a89ba0c64ec7e40e2bfa30a0618d104b Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/48564 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org --- A src/soc/amd/cezanne/include/soc/gpio.h 1 file changed, 285 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/include/soc/gpio.h b/src/soc/amd/cezanne/include/soc/gpio.h new file mode 100644 index 0000000..a97eee8 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/gpio.h @@ -0,0 +1,285 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_GPIO_H +#define AMD_CEZANNE_GPIO_H + +#define GPIO_DEVICE_NAME "AMD0030" +#define GPIO_DEVICE_DESC "GPIO Controller" + +#ifndef __ACPI__ +#include <soc/iomap.h> +#include <amdblocks/gpio_banks.h> + +/* The following sections describe only the GPIOs defined for this SOC */ + +#define SOC_GPIO_TOTAL_PINS 149 + +/* Bank 0: GPIO_0 - GPIO_63 */ +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_26 26 +#define GPIO_27 27 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 +#define GPIO_40 40 +#define GPIO_42 42 + +/* Bank 1: GPIO_64 - GPIO_127 */ +#define GPIO_67 67 +#define GPIO_68 68 +#define GPIO_69 69 +#define GPIO_70 70 +#define GPIO_74 74 +#define GPIO_75 75 +#define GPIO_76 76 +#define GPIO_84 84 +#define GPIO_85 85 +#define GPIO_86 86 +#define GPIO_87 87 +#define GPIO_88 88 +#define GPIO_89 89 +#define GPIO_90 90 +#define GPIO_91 91 +#define GPIO_92 92 +#define GPIO_104 104 +#define GPIO_105 105 +#define GPIO_106 106 +#define GPIO_107 107 +#define GPIO_108 108 +#define GPIO_109 109 +#define GPIO_113 113 +#define GPIO_114 114 +#define GPIO_115 115 +#define GPIO_116 116 +#define GPIO_120 120 +#define GPIO_121 121 + +/* Bank 2: GPIO_128 - GPIO_191 */ +#define GPIO_129 129 +#define GPIO_130 130 +#define GPIO_131 131 +#define GPIO_132 132 +#define GPIO_140 140 +#define GPIO_141 141 +#define GPIO_142 142 +#define GPIO_143 143 +#define GPIO_144 144 +#define GPIO_145 145 +#define GPIO_146 146 +#define GPIO_147 147 +#define GPIO_148 148 + +/* IOMUX function names and values */ +#define GPIO_0_IOMUX_PWR_BTN_L 0 +#define GPIO_0_IOMUX_GPIOxx 1 +#define GPIO_1_IOMUX_SYS_RESET_L 0 +#define GPIO_1_IOMUX_GPIOxx 1 +#define GPIO_2_IOMUX_WAKE_L 0 +#define GPIO_2_IOMUX_GPIOxx 1 +#define GPIO_3_IOMUX_GPIOxx 0 +#define GPIO_4_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_DEVSLP0 1 +#define GPIO_5_IOMUX_DEVSLP2 2 +#define GPIO_6_IOMUX_GPIOxx 0 +#define GPIO_6_IOMUX_DEVSLP1 1 +#define GPIO_6_IOMUX_DEVSLP3 2 +#define GPIO_7_IOMUX_GPIOxx 0 +#define GPIO_7_IOMUX_ACP_I2S_SDIN 1 +#define GPIO_8_IOMUX_GPIOxx 0 +#define GPIO_8_IOMUX_ACP_I2S_LRCLK 1 +#define GPIO_9_IOMUX_GPIOxx 0 +/* GPIO 9 IOMUX == 1 is reserved */ +#define GPIO_9_IOMUX_MDIO1_SCL 2 +#define GPIO_10_IOMUX_GPIOxx 0 +#define GPIO_10_IOMUX_S0A3 1 +/* GPIO 10 IOMUX == 2 is reserved */ +#define GPIO_10_IOMUX_MDIO0_SCL 3 +#define GPIO_11_IOMUX_GPIOxx 0 +#define GPIO_11_IOMUX_BLINK 1 +#define GPIO_12_IOMUX_LLB_L 0 +#define GPIO_12_IOMUX_GPIOxx 1 +#define GPIO_16_IOMUX_USB_OC0_L 0 +#define GPIO_16_IOMUX_GPIOxx 1 +#define GPIO_17_IOMUX_USB_OC1_L 0 +#define GPIO_17_IOMUX_GPIOxx 1 +#define GPIO_18_IOMUX_USB_OC2_L 0 +#define GPIO_18_IOMUX_GPIOxx 1 +#define GPIO_19_IOMUX_SCL1 0 +#define GPIO_19_IOMUX_I2C3_SCL 1 +#define GPIO_19_IOMUX_GPIOxx 2 +#define GPIO_20_IOMUX_SDA1 0 +#define GPIO_20_IOMUX_I2C3_SDA 1 +#define GPIO_20_IOMUX_GPIOxx 2 +#define GPIO_21_IOMUX_LPC_PD_L 0 +#define GPIO_21_IOMUX_EMMC_CMD 1 +#define GPIO_21_IOMUX_GPIOxx 2 +#define GPIO_22_IOMUX_LPC_PME_L 0 +#define GPIO_22_IOMUX_EMMC_PWR_CTRL 1 +#define GPIO_22_IOMUX_GPIOxx 2 +#define GPIO_23_IOMUX_AC_PRES 0 +/* GPIO 23 IOMUX == 1 is reserved */ +#define GPIO_23_IOMUX_MDIO1_SDA 2 +#define GPIO_23_IOMUX_GPIOxx 3 +#define GPIO_24_IOMUX_USB_OC3_L 0 +#define GPIO_24_IOMUX_GPIOxx 1 +#define GPIO_26_IOMUX_PCIE_RST_L 0 +#define GPIO_26_IOMUX_GPIOxx 1 +#define GPIO_27_IOMUX_GPIOxx 0 +#define GPIO_27_IOMUX_PCIE_RST1_L 1 +#define GPIO_29_IOMUX_SPI_TPM_CS_L 0 +#define GPIO_29_IOMUX_GPIOxx 1 +#define GPIO_30_IOMUX_SPI_CS2_L 0 +#define GPIO_30_IOMUX_ESPI_CS_L 1 +#define GPIO_30_IOMUX_GPIOxx 2 +#define GPIO_31_IOMUX_SPI_CS3_L 0 +#define GPIO_31_IOMUX_ESPI_CS_L 1 +#define GPIO_31_IOMUX_GPIOxx 2 +#define GPIO_32_IOMUX_LPC_RST_L 0 +#define GPIO_32_IOMUX_SD_WP_L 1 +#define GPIO_32_IOMUX_GPIOxx 2 +#define GPIO_40_IOMUX_GPIOxx 0 +/* GPIO 40 IOMUX == 1 is reserved */ +#define GPIO_40_IOMUX_MDIO0_SDA 2 +#define GPIO_42_IOMUX_GPIOxx 0 +#define GPIO_67_IOMUX_SPI_ROM_REQ 0 +#define GPIO_67_IOMUX_GPIOxx 1 +#define GPIO_68_IOMUX_GPIOxx 0 +#define GPIO_68_IOMUX_EMMC_CD 1 +#define GPIO_69_IOMUX_GPIOxx 0 +#define GPIO_70_IOMUX_GPIOxx 0 +#define GPIO_70_IOMUX_EMMC_CLK 1 +#define GPIO_70_IOMUX_SD_CLK 2 +#define GPIO_74_IOMUX_LPCCLK0 0 +#define GPIO_74_IOMUX_EMMC_DATA4 1 +#define GPIO_74_IOMUX_GPIOxx 2 +#define GPIO_75_IOMUX_LPCCLK1 0 +#define GPIO_75_IOMUX_EMMC_DATA6 1 +#define GPIO_75_IOMUX_GPIOxx 2 +#define GPIO_76_IOMUX_SPI_ROM_GNT 0 +#define GPIO_76_IOMUX_GPIOxx 1 +#define GPIO_84_IOMUX_FANIN0 0 +#define GPIO_84_IOMUX_GPIOxx 1 +#define GPIO_85_IOMUX_FANOUT0 0 +#define GPIO_85_IOMUX_GPIOxx 1 +#define GPIO_86_IOMUX_LPC_SMI_L 0 +#define GPIO_86_IOMUX_GPIOxx 1 +#define GPIO_86_IOMUX_SPI_CLK 2 +#define GPIO_87_IOMUX_SERIRQ 0 +#define GPIO_87_IOMUX_EMMC_DATA7 1 +#define GPIO_87_IOMUX_GPIOxx 2 +#define GPIO_88_IOMUX_LPC_CLKRUN_L 0 +#define GPIO_88_IOMUX_EMMC_DATA5 1 +#define GPIO_88_IOMUX_GPIOxx 2 +#define GPIO_89_IOMUX_GENINT1_L 0 +#define GPIO_89_IOMUX_PSP_INTR0 1 +#define GPIO_89_IOMUX_GPIOxx 2 +#define GPIO_90_IOMUX_GENINT2_L 0 +#define GPIO_90_IOMUX_PSP_INTR1 1 +#define GPIO_90_IOMUX_GPIOxx 2 +#define GPIO_91_IOMUX_SPKR 0 +#define GPIO_91_IOMUX_GPIOxx 1 +#define GPIO_92_IOMUX_CLK_REQ0_L 0 +#define GPIO_92_IOMUX_SATA_IS0_L 1 +#define GPIO_92_IOMUX_SATA_ZP0_L 2 +#define GPIO_92_IOMUX_GPIOxx 3 +#define GPIO_104_IOMUX_LAD0 0 +#define GPIO_104_IOMUX_SPI2_DO_ESPI2_D0 1 +#define GPIO_104_IOMUX_SD0_DATA0 2 +#define GPIO_104_IOMUX_GPIOxx 3 +#define GPIO_105_IOMUX_LAD1 0 +#define GPIO_105_IOMUX_SPI2_DI_ESPI2_D1 1 +#define GPIO_105_IOMUX_SD0_DATA1 2 +#define GPIO_105_IOMUX_GPIOxx 3 +#define GPIO_106_IOMUX_LAD2 0 +#define GPIO_106_IOMUX_EMMC_SPI2_WP_L_ESPI2_D2 1 +#define GPIO_106_IOMUX_EMMC_SD0_DATA2 2 +#define GPIO_106_IOMUX_GPIOxx 3 +#define GPIO_107_IOMUX_LAD3 0 +#define GPIO_107_IOMUX_SPI2_HOLD_L_ESPI2_D3 1 +#define GPIO_107_IOMUX_SD0_DATA3 2 +#define GPIO_107_IOMUX_GPIOxx 3 +#define GPIO_108_IOMUX_LDRQ0_L 0 +#define GPIO_108_IOMUX_ESPI_ALERT_D1 1 +#define GPIO_108_IOMUX_GPIOxx 2 +#define GPIO_109_IOMUX_LFRAME_L 0 +#define GPIO_109_IOMUX_EMMC_DS 1 +#define GPIO_109_IOMUX_GPIOxx 2 +#define GPIO_113_IOMUX_SCL0 0 +#define GPIO_113_IOMUX_I2C2_SCL 1 +#define GPIO_113_IOMUX_GPIOxx 2 +#define GPIO_114_IOMUX_SDA0 0 +#define GPIO_114_IOMUX_I2C2_SDA 1 +#define GPIO_114_IOMUX_GPIOxx 2 +#define GPIO_115_IOMUX_CLK_REQ1_L 0 +#define GPIO_115_IOMUX_GPIOxx 1 +#define GPIO_116_IOMUX_CLK_REQ2_L 0 +#define GPIO_116_IOMUX_GPIOxx 1 +#define GPIO_120_IOMUX_CLK_REQ5_L 0 +#define GPIO_120_IOMUX_GPIOxx 1 +#define GPIO_121_IOMUX_CLK_REQ6_L 0 +#define GPIO_121_IOMUX_GPIOxx 1 +#define GPIO_129_IOMUX_KBRST_L 0 +/* GPIO 129 IOMUX == 1 is reserved */ +#define GPIO_129_IOMUX_GPIOxx 2 +#define GPIO_130_IOMUX_SATA_ACT_L 0 +#define GPIO_130_IOMUX_GPIOxx 1 +#define GPIO_131_IOMUX_CLK_REQ3_L 0 +#define GPIO_131_IOMUX_SATA_IS1_L 1 +#define GPIO_131_IOMUX_SATA_ZP1_L 2 +#define GPIO_131_IOMUX_GPIOxx 3 +#define GPIO_132_IOMUX_CLK_REQ4_L 0 +#define GPIO_132_IOMUX_OSCIN 1 +#define GPIO_132_IOMUX_GPIOxx 2 +#define GPIO_140_IOMUX_GPIOxx 0 +#define GPIO_140_IOMUX_UART0_CTS_L 1 +#define GPIO_140_IOMUX_UART1_TXD 2 +#define GPIO_140_IOMUX_SD0_DATA1 3 +#define GPIO_141_IOMUX_GPIOxx 0 +#define GPIO_141_IOMUX_UART0_RXD 1 +#define GPIO_141_IOMUX_SD0_DATA3 2 +#define GPIO_142_IOMUX_GPIOxx 0 +#define GPIO_142_IOMUX_UART0_RTS_L 1 +#define GPIO_142_IOMUX_UART1_RXD 2 +#define GPIO_142_IOMUX_SD0_DATA0 3 +#define GPIO_143_IOMUX_GPIOxx 0 +#define GPIO_143_IOMUX_UART0_TXD 1 +#define GPIO_143_IOMUX_SD0_DATA2 2 +#define GPIO_144_IOMUX_GPIOxx 0 +/* GPIO 144 IOMUX == 1 is reserved */ +#define GPIO_144_IOMUX_UART0_INTR 2 +#define GPIO_145_IOMUX_I2C0_SCL 0 +#define GPIO_145_IOMUX_GPIOxx 1 +#define GPIO_146_IOMUX_I2C0_SDA 0 +#define GPIO_146_IOMUX_GPIOxx 1 +#define GPIO_147_IOMUX_I2C1_SCL 0 +#define GPIO_147_IOMUX_GPIOxx 1 +#define GPIO_148_IOMUX_I2C1_SDA 0 +#define GPIO_148_IOMUX_GPIOxx 1 + +#define GPIO_2_EVENT GEVENT_8 + +#endif /* !__ACPI__ */ +#endif /* AMD_CEZANNE_GPIO_H */
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