Change in coreboot[master]: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
2 files changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/1

diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc
index de92406..036b23c 100644
--- a/src/mainboard/intel/adlrvp/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/Makefile.inc
@@ -21,6 +21,11 @@
 ramstage-y += board_id.c
 ramstage-y += gpio.c

+cbfs-files-y += vbt_lp4.bin
+vbt_lp4.bin-file := 3rdparty/blobs/mainboard/intel/adlrvp_p/vbt_lp4.bin
+vbt_lp4.bin-type := raw
+vbt_lp4.bin-compression := lzma
+
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include

subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index fb25578..35385e3 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <device/device.h>
+#include <drivers/intel/gma/opregion.h>
 #include <ec/ec.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -38,3 +39,14 @@
    .init = mainboard_init,
    .enable_dev = mainboard_enable,
 };
+
+const char *mainboard_vbt_filename(void)
+{
+	uint8_t sku_id = get_board_id();
+	if (sku_id == 0x10) {
+		return "vbt_lp4.bin";
+	}
+	else {
+		return "vbt.bin";
+	}
+}

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 3:

(1 comment)

This change is ready for review.

https://review.coreboot.org/c/coreboot/+/48416/3/src/mainboard/intel/adlrvp/... 
File src/mainboard/intel/adlrvp/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/48416/3/src/mainboard/intel/adlrvp/... 
PS3, Line 25: 3rdparty/blobs/mainboard/intel/adlrvp_p/vbt_lp4.bin
3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt_lp4.bin

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 3:

HI Furquan,

Can you please suggest something here.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 3:
> Patch Set 3:
>
> HI Furquan,
>
> Can you please suggest something here.

This is how it was handled for drawman recently: https://crrev.com/i/3436383 and https://crrev.com/i/3439250

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 3:
> Patch Set 3:
> > Patch Set 3:
> >
> > HI Furquan,
> >
> > Can you please suggest something here.
>
> This is how it was handled for drawman recently: https://crrev.com/i/3436383 and https://crrev.com/i/3439250

so we can't add this into cb makefile directly ?

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 3:
> Patch Set 3:
> > Patch Set 3:
> > > Patch Set 3:
> > >
> > > HI Furquan,
> > >
> > > Can you please suggest something here.
> >
> > This is how it was handled for drawman recently: https://crrev.com/i/3436383 and https://crrev.com/i/3439250
>
> so we can't add this into cb makefile directly ?

You can do that, but you also have to add the .bin file here.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 3:
> Patch Set 3:
> > Patch Set 3:
> > > Patch Set 3:
> > > > Patch Set 3:
> > > >
> > > > HI Furquan,
> > > >
> > > > Can you please suggest something here.
> > >
> > > This is how it was handled for drawman recently: https://crrev.com/i/3436383 and https://crrev.com/i/3439250
> >
> > so we can't add this into cb makefile directly ?
>
> You can do that, but you also have to add the .bin file here.

That is what the error is:
"make[1]: *** No rule to make target '3rdparty/blobs/mainboard/intel/adlrvp_p/vbt_lp4.bin', needed by '/cb-build/coreboot-gerrit.0/chromeos/INTEL_ADLRVP_P/coreboot.pre'.  Stop."

[Meera Ravindranath (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48416

to look at the new patch set (#4).

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
3 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/4

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 3:

(1 comment)
> Patch Set 3:
> > Patch Set 3:
> > > Patch Set 3:
> > > > Patch Set 3:
> > > > > Patch Set 3:
> > > > >
> > > > > HI Furquan,
> > > > >
> > > > > Can you please suggest something here.
> > > >
> > > > This is how it was handled for drawman recently: https://crrev.com/i/3436383 and https://crrev.com/i/3439250
> > >
> > > so we can't add this into cb makefile directly ?
> >
> > You can do that, but you also have to add the .bin file here.
>
> That is what the error is:
> "make[1]: *** No rule to make target '3rdparty/blobs/mainboard/intel/adlrvp_p/vbt_lp4.bin', needed by '/cb-build/coreboot-gerrit.0/chromeos/INTEL_ADLRVP_P/coreboot.pre'.  Stop."

can we add like this to avoid the compilations issue

ifeq ($(CONFIG_INTEL_GMA_ADD_VBT),y)
cbfs-files-y += vbt_lp4.bin
vbt_lp4.bin-file := 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt_lp4.bin
vbt_lp4.bin-type := raw
vbt_lp4.bin-compression := lzma
endif

https://review.coreboot.org/c/coreboot/+/48416/3/src/mainboard/intel/adlrvp/... 
File src/mainboard/intel/adlrvp/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/48416/3/src/mainboard/intel/adlrvp/... 
PS3, Line 23: 
can we add like this

ifeq ($(CONFIG_INTEL_GMA_ADD_VBT),y)
cbfs-files-y += vbt_lp4.bin
vbt_lp4.bin-file := 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt_lp4.bin
vbt_lp4.bin-type := raw
vbt_lp4.bin-compression := lzma
endif

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48416/3/src/mainboard/intel/adlrvp/... 
File src/mainboard/intel/adlrvp/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/48416/3/src/mainboard/intel/adlrvp/... 
PS3, Line 23:
> can we add like this […]

What is the structure that you are trying to follow here? What will be supplying vbt_lp4.bin?

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48416/3/src/mainboard/intel/adlrvp/... 
File src/mainboard/intel/adlrvp/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/48416/3/src/mainboard/intel/adlrvp/... 
PS3, Line 23:
> What is the structure that you are trying to follow here? What will be supplying vbt_lp4. […]

LP4 SKU has DDI-A eDP and DDI-B DP
DDR5 and LP5 SKU has DDI-A eDP and DDI-B HDMI

so unified VBT is not an option

[Meera Ravindranath (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48416

to look at the new patch set (#5).

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
3 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/5

[Meera Ravindranath (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48416

to look at the new patch set (#6).

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
2 files changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/6

[Meera Ravindranath (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48416

to look at the new patch set (#7).

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
2 files changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/7

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 7: Code-Review+1

[Meera Ravindranath (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48416

to look at the new patch set (#8).

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/8

[Meera Ravindranath (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48416

to look at the new patch set (#9).

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/9

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 9:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48416/9/src/mainboard/intel/adlrvp/... 
File src/mainboard/intel/adlrvp/mainboard.c:

https://review.coreboot.org/c/coreboot/+/48416/9/src/mainboard/intel/adlrvp/... 
PS9, Line 46: 	switch(sku_id) {
space required before the open parenthesis '('

[Meera Ravindranath (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48416

to look at the new patch set (#10).

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/10

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 10: Code-Review+2

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 10: Code-Review+2

[Meera Ravindranath (Code Review)]

Attention is currently required from: Furquan Shaikh.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 12:

(2 comments)

File src/mainboard/intel/adlrvp/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/48416/comment/bc1e659d_66f80b99 
PS3, Line 23:
> LP4 SKU has DDI-A eDP and DDI-B DP […]

Ack

https://review.coreboot.org/c/coreboot/+/48416/comment/0d1e87de_4c9c4685 
PS3, Line 25: 3rdparty/blobs/mainboard/intel/adlrvp_p/vbt_lp4.bin
> 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt_lp4. […]

Ack

[Meera Ravindranath (Code Review)]

Attention is currently required from: Furquan Shaikh, Meera Ravindranath.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maulik V Vaghela, Subrata Banik, Sridhar Siricilla,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48416

to look at the new patch set (#15).

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU-ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
2 files changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/15

[Subrata Banik (Code Review)]

Attention is currently required from: Furquan Shaikh, Meera Ravindranath.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 15: Code-Review+2

[Furquan Shaikh (Code Review)]

Attention is currently required from: Meera Ravindranath.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 15:

(1 comment)

File src/mainboard/intel/adlrvp/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/48416/comment/1de4d325_d418b29a 
PS15, Line 22: add_vbt_to_cbfs= \
             : 	$(eval cbfs-files-y += $1) \
             : 	$(eval $1-file := $2) \
             : 	$(eval $1-type := raw) \
             : 	$(eval $1-compression := lzma)
This is already provided in https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/intel/gma/Mak.... Do you still need to define it again?

[Meera Ravindranath (Code Review)]

Attention is currently required from: Meera Ravindranath.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maulik V Vaghela, Subrata Banik, Sridhar Siricilla,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48416

to look at the new patch set (#16).

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU-ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
2 files changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48416/16

[Meera Ravindranath (Code Review)]

Attention is currently required from: Furquan Shaikh.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 16:

(1 comment)

File src/mainboard/intel/adlrvp/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/48416/comment/cfebc268_3563b61d 
PS15, Line 22: add_vbt_to_cbfs= \
             : 	$(eval cbfs-files-y += $1) \
             : 	$(eval $1-file := $2) \
             : 	$(eval $1-type := raw) \
             : 	$(eval $1-compression := lzma)
> This is already provided in https://review.coreboot.org/cgit/coreboot. […]

Thanks Furquan, removed it. Kindly review.

[Furquan Shaikh (Code Review)]

Attention is currently required from: Meera Ravindranath.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

Patch Set 16: Code-Review+2

(1 comment)

File src/mainboard/intel/adlrvp/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/48416/comment/3a544af2_b250ac3b 
PS16, Line 22: CONFIG_INTEL_GMA_ADD_VBT
Not for this change, but I think it would be good to evaluate if we can update CONFIG_INTEL_GMA_VBT_FILE to accept multiple files and loop through those to add to CBFS instead of just a single one.

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48416 )

Change subject: mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
......................................................................

mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs

Add support to pick the right vbt from cbfs according to
SKU-ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/mainboard/intel/adlrvp/Makefile.inc
M src/mainboard/intel/adlrvp/mainboard.c
2 files changed, 20 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc
index 75c8cf8..12f546b 100644
--- a/src/mainboard/intel/adlrvp/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/Makefile.inc
@@ -19,6 +19,11 @@
 ramstage-y += board_id.c
 ramstage-y += gpio.c

+ifeq ($(CONFIG_INTEL_GMA_ADD_VBT),y)
+$(call add_vbt_to_cbfs, vbt_lp5.bin, 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(VARIANT_DIR)/vbt_lp5.bin)
+$(call add_vbt_to_cbfs, vbt_ddr5.bin, 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(VARIANT_DIR)/vbt_ddr5.bin)
+endif
+
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include

subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index fb25578..3946204 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <device/device.h>
+#include <drivers/intel/gma/opregion.h>
 #include <ec/ec.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -38,3 +39,17 @@
    .init = mainboard_init,
    .enable_dev = mainboard_enable,
 };
+
+const char *mainboard_vbt_filename(void)
+{
+	uint8_t sku_id = get_board_id();
+	switch (sku_id) {
+	case ADL_P_LP5_1:
+	case ADL_P_LP5_2:
+		return "vbt_lp5.bin";
+	case ADL_P_DDR5:
+		return "vbt_ddr5.bin";
+	default:
+		return "vbt.bin";
+	}
+}