Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45354 )
Change subject: nb/intel/haswell: Move register headers into a subfolder ......................................................................
nb/intel/haswell: Move register headers into a subfolder
Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I143b3c829be44a39e14902255cd4bb13bf02f0c1 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/haswell.h R src/northbridge/intel/haswell/registers/host_bridge.h R src/northbridge/intel/haswell/registers/mchbar.h 3 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/45354/1
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 49e31a8..136701c 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -18,7 +18,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0)
-#include "hostbridge_regs.h" +#include "registers/host_bridge.h"
/* Device 0:2.0 PCI configuration space (Graphics Device) */ @@ -43,7 +43,7 @@ #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
/* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h"
#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ #define DMAR_LCKDN (1 << 31) diff --git a/src/northbridge/intel/haswell/hostbridge_regs.h b/src/northbridge/intel/haswell/registers/host_bridge.h similarity index 92% rename from src/northbridge/intel/haswell/hostbridge_regs.h rename to src/northbridge/intel/haswell/registers/host_bridge.h index 70e15b7..d348fd4 100644 --- a/src/northbridge/intel/haswell/hostbridge_regs.h +++ b/src/northbridge/intel/haswell/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __HASWELL_HOSTBRIDGE_REGS_H__ -#define __HASWELL_HOSTBRIDGE_REGS_H__ +#ifndef __HASWELL_REGISTERS_HOST_BRIDGE_H__ +#define __HASWELL_REGISTERS_HOST_BRIDGE_H__
#define EPBAR 0x40 #define MCHBAR 0x48 @@ -68,4 +68,4 @@
#define CAPID0_B 0xe8
-#endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */ +#endif /* __HASWELL_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/haswell/mchbar_regs.h b/src/northbridge/intel/haswell/registers/mchbar.h similarity index 91% rename from src/northbridge/intel/haswell/mchbar_regs.h rename to src/northbridge/intel/haswell/registers/mchbar.h index 5fe1556..d6e59ab 100644 --- a/src/northbridge/intel/haswell/mchbar_regs.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __HASWELL_MCHBAR_REGS_H__ -#define __HASWELL_MCHBAR_REGS_H__ +#ifndef __HASWELL_REGISTERS_MCHBAR_H__ +#define __HASWELL_REGISTERS_MCHBAR_H__
/* Register definitions */ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ @@ -44,4 +44,4 @@ #define DMIVCLIM 0x7000 #define CRDTLCK 0x77fc
-#endif /* __HASWELL_MCHBAR_REGS_H__ */ +#endif /* __HASWELL_REGISTERS_MCHBAR_H__ */
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45354 )
Change subject: nb/intel/haswell: Move register headers into a subfolder ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45354 )
Change subject: nb/intel/haswell: Move register headers into a subfolder ......................................................................
nb/intel/haswell: Move register headers into a subfolder
Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I143b3c829be44a39e14902255cd4bb13bf02f0c1 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45354 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/haswell.h R src/northbridge/intel/haswell/registers/host_bridge.h R src/northbridge/intel/haswell/registers/mchbar.h 3 files changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 49e31a8..136701c 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -18,7 +18,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0)
-#include "hostbridge_regs.h" +#include "registers/host_bridge.h"
/* Device 0:2.0 PCI configuration space (Graphics Device) */ @@ -43,7 +43,7 @@ #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
/* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h"
#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ #define DMAR_LCKDN (1 << 31) diff --git a/src/northbridge/intel/haswell/hostbridge_regs.h b/src/northbridge/intel/haswell/registers/host_bridge.h similarity index 92% rename from src/northbridge/intel/haswell/hostbridge_regs.h rename to src/northbridge/intel/haswell/registers/host_bridge.h index 70e15b7..d348fd4 100644 --- a/src/northbridge/intel/haswell/hostbridge_regs.h +++ b/src/northbridge/intel/haswell/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __HASWELL_HOSTBRIDGE_REGS_H__ -#define __HASWELL_HOSTBRIDGE_REGS_H__ +#ifndef __HASWELL_REGISTERS_HOST_BRIDGE_H__ +#define __HASWELL_REGISTERS_HOST_BRIDGE_H__
#define EPBAR 0x40 #define MCHBAR 0x48 @@ -68,4 +68,4 @@
#define CAPID0_B 0xe8
-#endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */ +#endif /* __HASWELL_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/haswell/mchbar_regs.h b/src/northbridge/intel/haswell/registers/mchbar.h similarity index 91% rename from src/northbridge/intel/haswell/mchbar_regs.h rename to src/northbridge/intel/haswell/registers/mchbar.h index 5fe1556..d6e59ab 100644 --- a/src/northbridge/intel/haswell/mchbar_regs.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __HASWELL_MCHBAR_REGS_H__ -#define __HASWELL_MCHBAR_REGS_H__ +#ifndef __HASWELL_REGISTERS_MCHBAR_H__ +#define __HASWELL_REGISTERS_MCHBAR_H__
/* Register definitions */ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ @@ -44,4 +44,4 @@ #define DMIVCLIM 0x7000 #define CRDTLCK 0x77fc
-#endif /* __HASWELL_MCHBAR_REGS_H__ */ +#endif /* __HASWELL_REGISTERS_MCHBAR_H__ */
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45354 )
Change subject: nb/intel/haswell: Move register headers into a subfolder ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19842 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19841 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/19840 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19839 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/19838 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19846 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/19845 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/19844 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/19843
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
Tim Wawrzynczak (Code Review)