Change in coreboot[master]: soc/amd/cezanne/Makefile.inc: Fix indentation

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50336 )

Change subject: soc/amd/cezanne/Makefile.inc: Fix indentation
......................................................................

soc/amd/cezanne/Makefile.inc: Fix indentation

We don't use spaces.

Signed-off-by: Raul E Rangel 
Change-Id: Id617e98db5b0895071ee98265f68f6106058bd63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50336
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
Reviewed-by: Angel Pons 
---
M src/soc/amd/cezanne/Makefile.inc
1 file changed, 5 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 45e98a5..7f59ef4 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -12,24 +12,24 @@
 bootblock-y	+= bootblock.c
 bootblock-y	+= early_fch.c
 bootblock-y	+= gpio.c
-bootblock-y     += reset.c
+bootblock-y	+= reset.c
 bootblock-y	+= uart.c

verstage_x86-y	+= gpio.c
-verstage_x86-y  += reset.c
+verstage_x86-y	+= reset.c
 verstage_x86-y	+= uart.c

romstage-y	+= gpio.c
-romstage-y      += reset.c
+romstage-y	+= reset.c
 romstage-y	+= romstage.c
 romstage-y	+= uart.c

ramstage-y	+= chip.c
 ramstage-y	+= fch.c
-ramstage-y      += fsp_params.c
+ramstage-y	+= fsp_params.c
 ramstage-y	+= gpio.c
 ramstage-y	+= pcie_gpp.c
-ramstage-y      += reset.c
+ramstage-y	+= reset.c
 ramstage-y	+= uart.c

CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include