[L] Change in coreboot[main]: soc/intel/cannonlake: Drop redundant PcieRpEnable

[Jonathon Hall (Code Review)]

Attention is currently required from: Christian Walter, Jeremy Soller, Michael Niewöhner, Michał Żygowski, Nick Vaccaro, Nico Huber, Patrick Rudolph, Piotr Król, Subrata Banik, Tim Crawford.

Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79918?usp=email )

Change subject: soc/intel/cannonlake: Drop redundant PcieRpEnable
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Patch Set 2:

(1 comment)

File src/mainboard/purism/librem_l1um_v2/bootblock.c:

https://review.coreboot.org/c/coreboot/+/79918/comment/995b76f7_7b6cf60c :
PS2, Line 15: #include <delay.h>
This brings back a duplicate #include that was recently cleaned up, please remove that again.

Rest looks fine to me, thanks