[M] Change in coreboot[main]: Documentation: Update console technotes

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86389?usp=email )

Change subject: Documentation: Update console technotes
......................................................................

Documentation: Update console technotes

coreboot wiki is no more. Using hints from Wayback Machine and
various sources within coreboot, replace the dead link with
actual content, updated with a modern take.

Change-Id: I83202a69a26b27bd92113e86d04f1a7b0adb1e6c
Signed-off-by: Keith Hui 
---
M Documentation/technotes/console.md
1 file changed, 95 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/86389/1

diff --git a/Documentation/technotes/console.md b/Documentation/technotes/console.md
index 363dfa5..9c028a4 100644
--- a/Documentation/technotes/console.md
+++ b/Documentation/technotes/console.md
@@ -1,8 +1,102 @@
 # coreboot Console

coreboot supports multiple ways to access its console.
-https://www.coreboot.org/Console_and_outputs

+## Serial Console
+
+This is the venerable RS232 serial port and has been the mainstay
+of coreboot console for as long as coreboot itself has been. It is
+also supported by many other coreboot payloads, such as SeaBIOS,
+GRUB, edk2, and more.
+
+USB serial port adapters however are not supported. For console
+output over USB you need EHCI debug port (see below).
+
+## EHCI Debug Port Console
+
+USB 2.0 (EHCI) has the ability to transfer debug output. Usually only
+on a specific port on the platform to simplify hardware design.
+
+First, a USB port with this support has to be located, along with the physical
+connector it connects to.
+A supported dongle is also required. Here are some examples:
+
+- A GNU/Linux computer with USB peripheral or OTG and the g_dbpg driver.
+  Single board computers typically have that.
+- Ajays NET20DC
+- AMIDebug RX
+
+Beyond coreboot, currently only GRUB and Linux kernel supports EHCI debug
+port logging.
+
+## USB Serial Port Console through EHCI Debug Port
+
+Similar to above, and currently only supported by a FTDI FT232H serial adapter.
+
+## spkmodem
+
+Beeps the console over an onboard speaker. Only coreboot itself and GRUB
+supports producing logs this way.
+
+A working sound card that can emit beeps during boot is needed. Most often this
+will be the basic PC speaker that dates back to the original IBM PC, which is
+integrated into the "southbridge" of modern PCs.
+
+On some laptops it's necessary to make sure the sound is enabled and the volume
+is correct to work. On many laptops it can be done beforehand in GNU/Linux.
+
+See `src/drivers/pc80/pc/spkmodem.c` for the tone patterns.
+
+Use the `spkmodem_recv` utility, available from the git repositories of both
+coreboot and GRUB, to receive the console output.
+
+## Network Console
+
+Sends console output over a NE2000 compatible ethernet card installed on the
+coreboot target system. Beyond coreboot the Linux kernel can also send logs
+this way.
+
+A second computer on the same network is needed to receive the logs. Use
+`nc` or similar networking utilities.
+
+## cbmem Console
+
+Stores the console output within cbmem, a reserved memory area carved out by
+coreboot for its various needs. The target computer must be able to boot
+fully to be able to retrieve the logs. SeaBIOS, edk2, and GRUB can also write
+logs to this space.
+
+To get the logs, use the `cbmem` utility, found in `util/cbmem` in the
+coreboot sources. GRUB can also get the log with the `cbmemc` command.
+
+## POST Card
+
+coreboot sends various 2-digit hex codes to port 0x80 during its boot process,
+a tradition that goes all the way back to the original IBM PC.
+
+Where and if POST codes are sent can be configured along with other compile time
+options during `make menuconfig`.
+
+Connect a POST card to display these codes, available for various interfaces.
+If the boot process dies, the last code written remains and should hint at
+where the problem is.
+
+There are caveats though for modern systems:
+
+- ISA POST cards: There are no longer any place for them.
+- PCI POST cards: Some PCI slots may be serviced by a PCIe-to-PCI bridge chip that
+  needs to be configured for subtractive decode. They most likely do not have enough
+  logic to positively claim port 0x80 on the PCI bus.
+- LPC POST cards: LPC port pinouts may vary and may be part of a TPM connector.
+  You may have to manually wire them to the port, although there's only 9 wires
+  in total. Some targets don't have a port for LPC bus at all.
+- PCIe POST cards: Still relatively expensive at $50+, and they may also need
+  the bus configured for subtractive decode similar to their PCI counterparts.
+
+Search the sources for `post_code` for the meaning of the codes. There should
+have been a central repository of POST codes in
+`commonlib/include/commonlib/console/post_codes.h`, but consolidation is far
+from complete.

## SMBus Console