[XS] Change in coreboot[main]: mb/starlabs/starfighter: Disable EC SCI and SMI GPIOs

[Sean Rhodes (Code Review)]

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84732?usp=email )

Change subject: mb/starlabs/starfighter: Disable EC SCI and SMI GPIOs
......................................................................

mb/starlabs/starfighter: Disable EC SCI and SMI GPIOs

This platform uses eSPI so these are not used; disable them.

Change-Id: Ied0ffb2999ef0582570b94d756c2fcbd131b7ccf
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84732
Reviewed-by: Matt DeVillier 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, approved

diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
index 286003a..ed38e34 100644
--- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
@@ -62,7 +62,7 @@
    /* A6:		Not Connected					*/
    PAD_NC(GPP_A6, NONE),
    /* A7:		Embedded Controller SCI				*/
-	PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, PLTRST, LEVEL),
+	PAD_NC(GPP_A7, NONE),
    /* A8:		Not Connected					*/
    PAD_NC(GPP_A8, NONE),
    /* A9:		ESPI Clock					*/
@@ -234,7 +234,7 @@
    /* D15:		Not Connected					*/
    PAD_NC(GPP_D15, NONE),
    /* D16:		PCH M.2 SSD Power Enable			*/
-PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
    /* D17:		Not used		Fingerprint ID		*/
    PAD_NC(GPP_D17, NONE),
    /* D18:		Trackpad reset					*/
@@ -259,7 +259,7 @@
    			High:	Enabled				*/
    PAD_CFG_GPO(GPP_E6, 0, DEEP),
    /* E7:		Embedded Controller SMI				*/
-	PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, DEEP, EDGE_SINGLE),
+	PAD_NC(GPP_E7, NONE),
    /* E8:		DRAM Sleep					*/
    PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
    /* E9:		USB OverCurrent 0				*/