[L] Change in coreboot[main]: SNB+MRC boards: Do not redo PEI data struct in hook

[Keith Hui (Code Review)]

Attention is currently required from: Alexander Couzens, Angel Pons, Martin L Roth.

Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76962?usp=email )

Change subject: SNB+MRC boards: Do not redo PEI data struct in hook
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Patch Set 5:

(1 comment)

File src/mainboard/google/butterfly/early_init.c:

https://review.coreboot.org/c/coreboot/+/76962/comment/e83e04ed_291d729a :
PS5, Line 100: 	/* TODO: Native raminit only uses 1333. Reconcile. */
> Acknowledged

I actually ran into the same problem as those Google boards on my p8z77-m with DDR3-1600 rated memory. None of them can boot at max_mem_clock 800mhz. Had to reduce it to 666 using your ternary and then somehow my best memory achieved same throughput as full speed. Maybe because it is running CL8 instead of CL9 at 800mhz clock...