Change in coreboot[master]: soc/intel/skylake: Check for supported UART index

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20997

Change subject: soc/intel/skylake: Check for supported UART index
......................................................................

soc/intel/skylake: Check for supported UART index

if UART index is 2 then Base address for LPSS UART2 is selected
else assert because skylake chrome design don't support legacy UART
selection.

Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/uart_debug.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20997/1

diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c
index f3d576b..20a2513 100644
--- a/src/soc/intel/skylake/uart_debug.c
+++ b/src/soc/intel/skylake/uart_debug.c
@@ -14,6 +14,7 @@
  */

#include <stddef.h>
+#include <console/console.h>
 #include <console/uart.h>
 #include <soc/iomap.h>
 #include <soc/serialio.h>
@@ -22,5 +23,8 @@
 {
    /* Same base address for all debug port usage. In reality UART2
     * is currently only supported. */
+	if (idx != 2)
+		die("unsupported UART index");
+
    return UART_DEBUG_BASE_ADDRESS;
 }