Change in coreboot[master]: mb/intel/shadowmountain: Add the ramstage code

[Aamir Bohra (Code Review)]

Attention is currently required from: V Sowmya, Martin Roth, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49732 )

Change subject: mb/intel/shadowmountain: Add the ramstage code
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Patch Set 3:

(1 comment)

File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/49732/comment/935fd2f2_5dc298fe 
PS3, Line 41: # Enable PCH PCIE RP 5 using CLK 1
            : 	register "PchPcieRpEnable[4]" = "1"
            : 	register "PcieClkSrcClkReq[1]" = "1"
            : 	register "PcieClkSrcUsage[1]" = "0x4"
            : 	register "PcieRpClkReqDetect[4]" = 
i think this would need a rebase as per https://review.coreboot.org/c/coreboot/+/48340