[S] Change in coreboot[master]: stoneyridge: Set the SPI read speed as 66MHz - coreboot-gerrit

18 Nov 2022


      Attention is currently required from: Bao Zheng, Jason Nien, Zheng Bao, Martin Roth.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68884 )
Change subject: stoneyridge: Set the SPI read speed as 66MHz
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68884/comment/74de6c79_05c1c2bf 
PS1, Line 7: stoneyridge: Set the SPI
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Isn't this changing the read MODE, not the speed? […]
this should be using dual io mode, since using the normal mode cuts the bandwidth in half. if Dual IO (1-2-2) is unstable, try Dual IO (1-1-2)
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ia6083cfa515abeb2e981ff0ef825970c9311466b
Gerrit-Change-Number: 68884
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