Change in coreboot[master]: soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Tim Crawford, Cliff Huang, Maulik V Vaghela, Patrick Rudolph, EricR Lai.
Hello Tim Crawford, build bot (Jenkins), Cliff Huang, Subrata Banik, Maulik V Vaghela, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60182

to look at the new patch set (#5).

Change subject: soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs
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soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs

The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe
ports, but the UPDs are not set. This patch hooks up those config
structs to the appropriate FSP-S UPDs.

Signed-off-by: Tim Wawrzynczak 
Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/60182/5