Change in coreboot[master]: mb/intel/tglrvp: Enable TPM

[Anil Kumar K (Code Review)]

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Enable TPM
......................................................................

mb/intel/tglrvp: Enable TPM

Bug=none
Test=emerge build successful on tglrvpwq

Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/drivers/spi/tpm/tpm.c
M src/mainboard/intel/tglrvp/Kconfig
2 files changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/1

diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c
index 4263dce..bc9f06e 100644
--- a/src/drivers/spi/tpm/tpm.c
+++ b/src/drivers/spi/tpm/tpm.c
@@ -157,6 +157,8 @@
    for (i = 0; i < 3; i++)
    	header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff;

+	udelay(100);
+
    /* CS assert wakes up the slave. */
    spi_claim_bus(&spi_slave);

diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig
index eeeecc1..e4c29f8 100644
--- a/src/mainboard/intel/tglrvp/Kconfig
+++ b/src/mainboard/intel/tglrvp/Kconfig
@@ -18,6 +18,9 @@
    select DRIVERS_INTEL_ISH
    select EC_ACPI
    select PCIEXP_HOTPLUG
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_HAS_SPI_TPM_CR50
+	select SPI_TPM

config CHROMEOS
    bool
@@ -100,9 +103,12 @@

config VBOOT
    select VBOOT_LID_SWITCH
-	select VBOOT_MOCK_SECDATA

config UART_FOR_CONSOLE
    int
    default 2
+
+config DRIVER_TPM_SPI_BUS
+        default 0x2
+
 endif

[Anil Kumar K (Code Review)]

Hello build bot (Jenkins), Christian Walter,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44698

to look at the new patch set (#2).

Change subject: mb/intel/tglrvp: Enable TPM
......................................................................

mb/intel/tglrvp: Enable TPM

Bug=none
Test=emerge build successful on tglrvpwq

Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/drivers/spi/tpm/tpm.c
M src/mainboard/intel/tglrvp/Kconfig
2 files changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/2

[Anil Kumar K (Code Review)]

Hello build bot (Jenkins), Christian Walter,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44698

to look at the new patch set (#3).

Change subject: mb/intel/tglrvp: Enable TPM
......................................................................

mb/intel/tglrvp: Enable TPM

Bug=none
Test=emerge build successful on tglrvpwq

Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/drivers/spi/tpm/tpm.c
M src/mainboard/intel/tglrvp/Kconfig
2 files changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/3

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Enable TPM
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44698/3/src/drivers/spi/tpm/tpm.c 
File src/drivers/spi/tpm/tpm.c:

https://review.coreboot.org/c/coreboot/+/44698/3/src/drivers/spi/tpm/tpm.c@1... 
PS3, Line 160: 	udelay(100);
Is this a WIP test patch? You can't just insert random delays into a core driver to work around bugs with your platform...

Change in coreboot[master]: [WIP] mb/intel/tglrvp: Enable TPM

[Anil Kumar K (Code Review)]

Hello build bot (Jenkins), Christian Walter,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44698

to look at the new patch set (#4).

Change subject: [WIP] mb/intel/tglrvp: Enable TPM
......................................................................

[WIP] mb/intel/tglrvp: Enable TPM

Bug=none
Test=emerge build successful on tglrvpwq

Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/drivers/spi/tpm/tpm.c
M src/mainboard/intel/tglrvp/Kconfig
2 files changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/4

Change in coreboot[master]: [WIP] mb/intel/tglrvp: Add support of TPM over SPI

[Shaunak Saha (Code Review)]

Shaunak Saha has uploaded a new patch set (#5) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: [WIP] mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

[WIP] mb/intel/tglrvp: Add support of TPM over SPI

Bug=none
Test=emerge build and boot on tglrvp and check that
tpm is probed successfully from coreboot.

Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/mainboard/intel/tglrvp/Kconfig
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
5 files changed, 63 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/5

Change in coreboot[master]: [WIP] mb/intel/tglrvp: Add support of TPM over SPI

[Shaunak Saha (Code Review)]

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: [WIP] mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44698/3/src/drivers/spi/tpm/tpm.c 
File src/drivers/spi/tpm/tpm.c:

https://review.coreboot.org/c/coreboot/+/44698/3/src/drivers/spi/tpm/tpm.c@1... 
PS3, Line 160: 	udelay(100);
> Is this a WIP test patch? You can't just insert random delays into a core driver to work around bugs […]

We removed the delay. Agreed we cannot put delay in common code.

Change in coreboot[master]: [WIP] mb/intel/tglrvp: Add support of TPM over SPI

[Shaunak Saha (Code Review)]

Shaunak Saha has uploaded a new patch set (#6) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: [WIP] mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

[WIP] mb/intel/tglrvp: Add support of TPM over SPI

Bug=none
Test=emerge build and boot on tglrvp and check that
tpm is probed successfully from coreboot.

Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/mainboard/intel/tglrvp/Kconfig
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
5 files changed, 65 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/6

Change in coreboot[master]: [WIP] mb/intel/tglrvp: Add support of TPM over SPI

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#8) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: [WIP] mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

[WIP] mb/intel/tglrvp: Add support of TPM over SPI

Bug=none
Test=emerge build and boot on tglrvp and check that
tpm is probed successfully from coreboot.

Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/mainboard/intel/tglrvp/Kconfig
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
5 files changed, 65 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/8

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#9) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

mb/intel/tglrvp: Add support of TPM over SPI

Bug=none
Test=emerge build and boot on tglrvp and check that
tpm is probed successfully from coreboot.

Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/mainboard/intel/tglrvp/Kconfig
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
5 files changed, 65 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/9

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

Patch Set 9: Code-Review+1

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

Patch Set 9:

Please rebase.

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#10) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

mb/intel/tglrvp: Add support of TPM over SPI

Bug=none
Test=emerge build and boot on tglrvp and check that
tpm is probed successfully from coreboot.

Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/mainboard/intel/tglrvp/Kconfig
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
5 files changed, 65 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/10

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

Patch Set 10: Code-Review+2

If you think needed, please add verbatim describing commit changes.

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#11) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

mb/intel/tglrvp: Add support of TPM over SPI

Bug=none
Test=emerge build and boot on tglrvp and check that
tpm is probed successfully from coreboot.

Cq-Depend:chromium-review:1881839
Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
---
M src/mainboard/intel/tglrvp/Kconfig
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
5 files changed, 65 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44698/11

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

Patch Set 11:
> Patch Set 9:
>
> Please rebase.

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

Patch Set 11:

Hi Tim, locally RVP build passes. But in Jenkins, I see errors and them seem unrelated to this change. Could you please help to check if you can find the reason?
https://qa.coreboot.org/job/coreboot-gerrit/144804/console

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

Patch Set 11:

It passed now.

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

Patch Set 11: Code-Review+2

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44698/3/src/drivers/spi/tpm/tpm.c 
File src/drivers/spi/tpm/tpm.c:

https://review.coreboot.org/c/coreboot/+/44698/3/src/drivers/spi/tpm/tpm.c@1... 
PS3, Line 160: 	udelay(100);
> We removed the delay. Agreed we cannot put delay in common code.

Done

Change in coreboot[master]: mb/intel/tglrvp: Add support of TPM over SPI

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44698 )

Change subject: mb/intel/tglrvp: Add support of TPM over SPI
......................................................................

mb/intel/tglrvp: Add support of TPM over SPI

Bug=none
Test=emerge build and boot on tglrvp and check that
tpm is probed successfully from coreboot.

Cq-Depend:chromium-review:1881839
Signed-off-by: Anil Kumar 
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44698
Tested-by: build bot (Jenkins) 
Reviewed-by: Srinidhi N Kaushik 
Reviewed-by: Ravishankar Sarawadi 
---
M src/mainboard/intel/tglrvp/Kconfig
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
5 files changed, 65 insertions(+), 13 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Ravishankar Sarawadi: Looks good to me, approved
  Srinidhi N Kaushik: Looks good to me, approved

diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig
index 26e5966..2ded178 100644
--- a/src/mainboard/intel/tglrvp/Kconfig
+++ b/src/mainboard/intel/tglrvp/Kconfig
@@ -21,6 +21,9 @@
    select PCIEXP_HOTPLUG
    select HAVE_SPD_IN_CBFS
    select SOC_INTEL_CSE_LITE_SKU
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_HAS_SPI_TPM_CR50
+	select SPI_TPM

config CHROMEOS
    bool
@@ -102,9 +105,16 @@

config VBOOT
    select VBOOT_LID_SWITCH
-	select VBOOT_MOCK_SECDATA

config UART_FOR_CONSOLE
    int
    default 2
+
+config DRIVER_TPM_SPI_BUS
+	default 0x2
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 54  # GPE0_DW1_22 (GPP_C22)
+
 endif
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index ad7eabe..384bc1b 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -9,8 +9,8 @@
    # route. i.e. If this route changes then the affected GPE
    # offset bits also need to be changed.
    register "pmc_gpe0_dw0" = "GPP_B"
-	register "pmc_gpe0_dw1" = "GPP_D"
-	register "pmc_gpe0_dw2" = "GPP_E"
+	register "pmc_gpe0_dw1" = "GPP_C"
+	register "pmc_gpe0_dw2" = "GPP_D"

# Enable heci1 communication
    register "HeciEnabled" = "1"
@@ -86,14 +86,14 @@

register "SerialIoGSpiMode" = "{
    	[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
    	[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
    	[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
    }"

register "SerialIoGSpiCsMode" = "{
    	[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI1] = 1,
    	[PchSerialIoIndexGSPI2] = 0,
    	[PchSerialIoIndexGSPI3] = 0,
    }"
@@ -152,6 +152,10 @@
    # Intel Common SoC Config
    register "common_soc_config" = "{
    	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[1] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
    	.i2c[0] = {
    		.speed = I2C_SPEED_FAST,
    	},
@@ -294,8 +298,15 @@
    	device pci 1d.3 off end # RP12			0xA0B3
    	device pci 1e.0 off end # UART0			0xA0A8
    	device pci 1e.1 off end # UART1			0xA0A9
-		device pci 1e.2 off end # GSPI0			0xA0AA
-		device pci 1e.3 off end # GSPI1			0xA0AB
+		device pci 1e.2 on end # GSPI0			0xA0AA
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI1					0xA0AB
    	device pci 1f.0 on
    		chip ec/google/chromeec
    			device pnp 0c09.0 on end
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
index 49946c8..c9de9c6 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -94,6 +94,16 @@
    PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */
    PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */
    PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */
+
+	/* TPM */
+	/* B19 : GSPI1_CS0B */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+	/* B20 : GSPI1_CLK */
+	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+	/* B21 : GSPI1_MISO */
+	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+	/* B22 : GSPI1_MOSI */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
 };

const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 842ae68..410d06b 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -9,8 +9,8 @@
    # route. i.e. If this route changes then the affected GPE
    # offset bits also need to be changed.
    register "pmc_gpe0_dw0" = "GPP_B"
-	register "pmc_gpe0_dw1" = "GPP_D"
-	register "pmc_gpe0_dw2" = "GPP_E"
+	register "pmc_gpe0_dw1" = "GPP_C"
+	register "pmc_gpe0_dw2" = "GPP_D"

# Enable heci1 communication
    register "HeciEnabled" = "1"
@@ -90,14 +90,14 @@

register "SerialIoGSpiMode" = "{
    	[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
-		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
    	[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
    	[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
    }"

register "SerialIoGSpiCsMode" = "{
    	[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI1] = 1,
    	[PchSerialIoIndexGSPI2] = 0,
    	[PchSerialIoIndexGSPI3] = 0,
    }"
@@ -156,6 +156,10 @@
    # Intel Common SoC Config
    register "common_soc_config" = "{
    	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[1] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
    	.i2c[0] = {
    		.speed = I2C_SPEED_FAST,
    	},
@@ -298,8 +302,15 @@
    	device pci 1d.3 off end # RP12			0xA0B3
    	device pci 1e.0 off end # UART0			0xA0A8
    	device pci 1e.1 off end # UART1			0xA0A9
-		device pci 1e.2 off end # GSPI0			0xA0AA
-		device pci 1e.3 off end # GSPI1			0xA0AB
+		device pci 1e.2 on end # GSPI0			0xA0AA
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI1					0xA0AB
    	device pci 1f.0 on
    		chip ec/google/chromeec
    			device pnp 0c09.0 on end
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
index 91bbe93..303350b 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
@@ -90,6 +90,16 @@
    PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */
    PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */
    PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */
+
+	/* TPM */
+	/* B19 : GSPI1_CS0B */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+	/* B20 : GSPI1_CLK */
+	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+	/* B21 : GSPI1_MISO */
+	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+	/* B22 : GSPI1_MOSI */
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
 };

const struct pad_config *variant_gpio_table(size_t *num)