[M] Change in coreboot[main]: drivers/intel/gma/opregion: Use CBFS cache to load VBT

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77886?usp=email )

Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT
......................................................................

drivers/intel/gma/opregion: Use CBFS cache to load VBT

Thanks to x86 CBFS cache support, we can leverage cbfs_map() function
to load the VBT binary regardless of if it is compressed or not.

Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7
Signed-off-by: Jeremy Compostella 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886
Tested-by: build bot (Jenkins) 
Reviewed-by: Julius Werner 
---
M src/drivers/intel/gma/Kconfig
M src/drivers/intel/gma/opregion.c
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/tigerlake/Kconfig
6 files changed, 25 insertions(+), 46 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved

diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig
index 47f7617..ca0143d 100644
--- a/src/drivers/intel/gma/Kconfig
+++ b/src/drivers/intel/gma/Kconfig
@@ -59,10 +59,6 @@
 config INTEL_GMA_LIBGFXINIT_EDID
    bool

-config VBT_DATA_SIZE_KB
-	int
-	default 8
-
 config VBT_CBFS_COMPRESSION_DEFAULT_LZ4
    def_bool n
    help
diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
index fe333fa..d551638 100644
--- a/src/drivers/intel/gma/opregion.c
+++ b/src/drivers/intel/gma/opregion.c
@@ -19,40 +19,39 @@
    return "vbt.bin";
 }

-static char vbt_data[CONFIG_VBT_DATA_SIZE_KB * KiB];
-static size_t vbt_data_sz;
-
 void *locate_vbt(size_t *vbt_size)
 {
-	uint32_t vbtsig = 0;
+	static void *data;
+	static size_t size;

-	if (vbt_data_sz != 0) {
-		if (vbt_size)
-			*vbt_size = vbt_data_sz;
-		return (void *)vbt_data;
+	if (data)
+		goto out;
+
+	data = cbfs_map(mainboard_vbt_filename(), &size);
+	if (!data || size == 0) {
+		printk(BIOS_ERR, "Could not find or load %s CBFS file\n",
+		       mainboard_vbt_filename());
+		goto err;
    }

-	const char *filename = mainboard_vbt_filename();
-
-	size_t file_size = cbfs_load(filename, vbt_data, sizeof(vbt_data));
-
-	if (file_size == 0)
-		return NULL;
-
-	if (vbt_size)
-		*vbt_size = file_size;
-
-	memcpy(&vbtsig, vbt_data, sizeof(vbtsig));
-	if (vbtsig != VBT_SIGNATURE) {
-		printk(BIOS_ERR, "Missing/invalid signature in VBT data file!\n");
-		return NULL;
+	if (*(uint32_t *)data == VBT_SIGNATURE) {
+		printk(BIOS_INFO, "Found a VBT of %zu bytes\n", size);
+		goto out;
    }

-	printk(BIOS_INFO, "Found a VBT of %zu bytes after decompression\n",
-		file_size);
-	vbt_data_sz = file_size;
+	printk(BIOS_ERR, "Missing/invalid signature in VBT data file!\n");

-	return (void *)vbt_data;
+err:
+	if (data) {
+		cbfs_unmap(data);
+		data = NULL;
+	}
+	size = 0;
+
+out:
+	if (vbt_size && size)
+		*vbt_size = size;
+	return data;
 }

/* Write ASLS PCI register and prepare SWSCI register. */
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 251695e..eea27fc 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -350,10 +350,6 @@
    default 0xfe03e000
    depends on INTEL_LPSS_UART_FOR_CONSOLE

-config VBT_DATA_SIZE_KB
-	int
-	default 9
-
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clock * M) /(N *16)
 # ADL UART source clock: 100MHz
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 3d84991..9f70177 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -174,10 +174,6 @@
    hex
    default 0xc35

-config VBT_DATA_SIZE_KB
-	int
-	default 9
-
 config VBOOT
    select VBOOT_MUST_REQUEST_DISPLAY
    select VBOOT_STARTS_IN_BOOTBLOCK
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index d0db3e2..05d7f70 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -301,10 +301,6 @@
    default 0xfe02c000
    depends on INTEL_LPSS_UART_FOR_CONSOLE

-config VBT_DATA_SIZE_KB
-	int
-	default 9
-
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clock * M) /(N *16)
 # MTL UART source clock: 100MHz
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index c07a0d8..2d5cf08 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -222,10 +222,6 @@
    hex
    default 0x7fff

-config VBT_DATA_SIZE_KB
-	int
-	default 9
-
 config VBOOT
    select VBOOT_MUST_REQUEST_DISPLAY
    select VBOOT_STARTS_IN_BOOTBLOCK