Patch set updated for coreboot: soc/intel/skylake: Fix top_of_ram calculation

[Naresh Solanki]

Naresh Solanki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17554

-gerrit

commit 5b9c8c929dc63d268b5fe483aa0137a02b51ba69
Author: Naresh G Solanki 
Date:   Wed Nov 16 21:32:04 2016 +0530

soc/intel/skylake: Fix top_of_ram calculation

FSP 2.0 implementation conditionally sets PMRR base based on
    EnableC6Dram UPD. Therefore, handle the case of the PMRR base not being
    set since FSP 2.0 changed behavior from FSP 1.1 implementation.

If prmrr base is non-zero value, then top_of_ram is prmrr base.

If Probeless trace is enabled, then deduct trace memory size from
    calculated top_of_ram.

Change-Id: I2633bf78705e36b241668a313d215d0455fba607
    Signed-off-by: Rizwan Qureshi 
    Signed-off-by: Naresh G Solanki 
---
 src/soc/intel/skylake/memmap.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 96debfd..17dbc32 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -150,7 +150,8 @@ u32 top_of_32bit_ram(void)
     * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before
     * PRMRR_MASK MSR lock bit is set.
     */
-	if (smm_region_start() == 0)
+	top_of_ram = smm_region_start();
+	if (top_of_ram == 0)
    	return 0;

dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));
@@ -163,7 +164,8 @@ u32 top_of_32bit_ram(void)
     * Refer to Fsp Integration Guide for the memory mapping layout.
     */
    prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);
-	top_of_ram = prmrr_base.lo;
+	if (prmrr_base.lo)
+		top_of_ram = prmrr_base.lo;

if (config->ProbelessTrace)
    	top_of_ram -= TRACE_MEMORY_SIZE;