build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27407 )
Change subject: src/northbridge: Use "foo *bar" instead of "foo* bar" ......................................................................
Patch Set 1:
(33 comments)
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... File src/northbridge/amd/amdmct/mct_ddr3/mct_d.h:
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 1058: void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 1059: void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 1136: void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... File src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c:
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 320: static void read_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 349: static void write_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... File src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c:
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 258: void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 285: static void write_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 317: static void write_write_data_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 356: void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 390: void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 427: static void read_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 459: static void write_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 497: void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 531: void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 272: static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t *restored) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 306: void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_data) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 329: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 597: void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t training_only) line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 611: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 655: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 666: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 722: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 761: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 826: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 871: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 912: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 929: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 967: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 986: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 1013: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 1037: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 1069: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
https://review.coreboot.org/#/c/27407/1/src/northbridge/amd/amdmct/mct_ddr3/... PS1, Line 1084: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters
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