Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31832 )
Change subject: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant ......................................................................
Patch Set 9: Code-Review+2
(2 comments)
https://review.coreboot.org/#/c/31832/9/src/mainboard/gigabyte/ga-h61m-s2pv/... File src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c:
https://review.coreboot.org/#/c/31832/9/src/mainboard/gigabyte/ga-h61m-s2pv/... PS9, Line 31: pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); I guess routing CNF2 (for 0x4e) is not really needed here. And without COMB_LPC_EN set programming LPC_IO_DEC is not really needed either.
https://review.coreboot.org/#/c/31832/9/src/mainboard/gigabyte/ga-h61m-s2pv/... File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb:
https://review.coreboot.org/#/c/31832/9/src/mainboard/gigabyte/ga-h61m-s2pv/... PS9, Line 85: io 0x64 = 0x0000 I am not sure how resource allocator treats these IO base 0x0 entries. From what I remember, we generally don't have a range/size associated for these anyways, so probably they just get ignored.
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Kyösti Mälkki (Code Review)