Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49871 )
Change subject: mb/intel/adlrvp_m: Add initial code for adl-m variant board ......................................................................
mb/intel/adlrvp_m: Add initial code for adl-m variant board
List of changes: 1. Add mainboard Kconfig to Kconfig.name files 2. Handle mainboard names in Kconfig file for adlrvp 3. Created a new devicetree.cb for Adlrvp-m. 3. Add override devicetree for ADL-M RVP. 4. Configure proper PCI and USB ports as per schematics for ADL-M
BUG=None BRANCH=None TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec.
Signed-0ff-by: Maulik Vaghela maulik.v.vaghela@intel.com Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49871 Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Ronak Kanabar ronak.kanabar@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Kconfig.name A src/mainboard/intel/adlrvp/devicetree_m.cb A src/mainboard/intel/adlrvp/variants/adlrvp_m/overridetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb 5 files changed, 317 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Ronak Kanabar: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 80d5254..ee2dede 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC +if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -9,10 +9,11 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_INTEL_SOUNDWIRE - select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC + select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select SOC_INTEL_ALDERLAKE + select SOC_INTEL_ALDERLAKE_PCH_M if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC select HAVE_SPD_IN_CBFS select DRIVERS_SOUNDWIRE_ALC711 select PCIEXP_HOTPLUG @@ -33,10 +34,13 @@ string default "adlrvp_p" if BOARD_INTEL_ADLRVP_P default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC + default "adlrvp_m" if BOARD_INTEL_ADLRVP_M + default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC
config GBB_HWID string depends on CHROMEOS + default "ADLRVPM" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC default "ADLRVPP"
config MAINBOARD_PART_NUMBER @@ -47,6 +51,11 @@ string default "Intel_adlrvp"
+config DEVICETREE + string + default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC + default "devicetree.cb" + config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -57,8 +66,8 @@
choice prompt "ON BOARD EC" - default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P - default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC + default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M + default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC help This option allows you to select the on board EC to use. Select whether the board has Intel EC or Chrome EC diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name index 0d54bb9..743253e 100644 --- a/src/mainboard/intel/adlrvp/Kconfig.name +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -6,3 +6,12 @@ config BOARD_INTEL_ADLRVP_P_EXT_EC bool "Alderlake-P RVP with Chrome EC" select INTEL_LPSS_UART_FOR_CONSOLE + +config BOARD_INTEL_ADLRVP_M + bool "Alderlake-M RVP" + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + +config BOARD_INTEL_ADLRVP_M_EXT_EC + bool "Alderlake-M RVP with Chrome EC" + select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb new file mode 100644 index 0000000..3094010 --- /dev/null +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -0,0 +1,265 @@ +chip soc/intel/alderlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A port 1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Type-A port 2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "gen4_dec" = "0x000c0081" + + register "PrmrrSize" = "0" + + #Enable PCH PCIE RP 4 using CLK 5 + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 5 using CLK 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 9 using CLK 3 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + #Enable PCH PCIE RP 10 using CLK 1 + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Hybrid storage mode + register "HybridStorageMode" = "1" + + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + }" + + # Enable EDP in PortA + register "DdiPortAConfig" = "1" + # Enable HDMI in Port B + register "DdiPortBDdc" = "1" + register "DdiPortBHpd" = "1" + + # TCSS USB3 + register "TcssAuxOri" = "0" + + register "s0ix_enable" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" + register "PchHdaAudioLinkSndwEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 on end # PEG10 + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 on end # IPU + device pci 06.0 on end # PEG60 + device pci 06.2 on end # PEG62 + device pci 07.0 on end # TBT_PCIe0 + device pci 07.1 on end # TBT_PCIe1 + device pci 07.2 on end # TBT_PCIe2 + device pci 07.3 on end # TBT_PCIe3 + device pci 08.0 off end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 on end # USB xDCI (OTG) + device pci 0d.2 on end # TBT DMA0 + device pci 0d.3 on end # TBT DMA1 + device pci 0e.0 off end # VMD + device pci 10.0 off end + device pci 10.1 off end + device pci 10.2 on end # CNVi: BT + device pci 10.6 off end # THC0 + device pci 10.7 off end # THC1 + device pci 11.0 off end + device pci 11.1 off end + device pci 11.2 off end + device pci 11.3 off end + device pci 11.4 off end + device pci 11.5 off end + device pci 12.0 off end # SensorHUB + device pci 12.5 off end + device pci 12.6 off end # GSPI2 + device pci 13.0 off end # GSPI3 + device pci 13.1 off end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + end + end + end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI + device pci 14.2 off end # Shared RAM + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + device pci 16.0 on end # HECI1 + device pci 16.1 off end # HECI2 + device pci 16.2 off end # CSME + device pci 16.3 off end # CSME + device pci 16.4 off end # HECI3 + device pci 16.5 off end # HECI4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 off end # UART2 + device pci 1c.0 on end # RP1 + device pci 1c.1 off end # RP2 + device pci 1c.2 on end # RP3 # W/A to FSP issue + device pci 1c.3 on end # RP4 # W/A to FSP issue + device pci 1c.4 on end # RP5 + device pci 1c.5 on end # RP6 + device pci 1c.6 off end # RP7 + device pci 1c.7 on end # RP8 + device pci 1d.0 on end # RP9 + device pci 1d.1 on end # RP10 + device pci 1d.2 off end # RP11 + device pci 1d.3 off end # RP12 + device pci 1e.0 on end # UART0 + device pci 1e.1 off end # UART1 + device pci 1e.2 on end # GSPI0 + device pci 1e.3 off end # GSPI1 + device pci 1f.0 on end # eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # PMC + device pci 1f.3 on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + end + end + end # Intel Audio SNDW + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TH + end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m/overridetree.cb new file mode 100644 index 0000000..cb9c3fc --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m/overridetree.cb @@ -0,0 +1,3 @@ +chip soc/intel/alderlake + device domain 0 on end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb new file mode 100644 index 0000000..80450e7 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb @@ -0,0 +1,27 @@ +chip soc/intel/alderlake + device domain 0 on + device pci 1f.2 hidden + + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "1" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "2" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end # PMC + end +end
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Patrick Georgi (Code Review)