Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
mb/asrock/h110m: Remove zeroed options from devicetree
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Ic39b4c70ccb9ec21780c937322d63820064abbd1 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/49185/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index ffa35f7..d291ad5 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -2,10 +2,6 @@
chip soc/intel/skylake
- register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_WAKE_PIN"
register "eist_enable" = "1" @@ -138,7 +134,6 @@ device pci 01.0 on # PEG subsystemid 0x1849 0x1901 register "Peg0MaxLinkWidth" = "Peg0_x16" - register "SkipExtGfxScan" = "0"
# Configure PCIe clockgen in PCH register "PcieRpClkReqSupport[0]" = "1" @@ -189,7 +184,6 @@ device pci 15.3 off end # I2C #3 device pci 16.0 off # Management Engine Interface 1 subsystemid 0x1849 0xa131 - register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -378,7 +372,6 @@ device pci 1f.2 on end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaVcType" = "Vc1" - register "DspEnable" = "0" end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI
Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
mb/asrock/h110m: Remove zeroed options from devicetree
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Ic39b4c70ccb9ec21780c937322d63820064abbd1 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/49185/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
Patch Set 3: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 5: register "deep_sx_config" = "DSX_EN_WAKE_PIN" when dsx is disabled, this one can be dropped, too; either in this change (because it's directly related. just mention it in the commit msg then) or in a separate change.
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 36: : # VR Settings Configuration : #+----------------+-------+-------+-------------+-------+ : #| Domain/Setting | SA | IA | GT Unsliced | GT | : #+----------------+-------+-------+-------------+-------+ : #| Psi1Threshold | 20A | 20A | 20A | 20A | : #| Psi2Threshold | 4A | 5A | 5A | 5A | : #| Psi3Threshold | 1A | 1A | 1A | 1A | : #| Psi3Enable | 1 | 1 | 1 | 1 | : #| Psi4Enable | 1 | 1 | 1 | 1 | : #| ImonSlope | 0 | 0 | 0 | 0 | : #| ImonOffset | 0 | 0 | 0 | 0 | : #| IccMax* | 0 | 0 | 0 | 0 | : #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | : #+----------------+-------+-------+-------------+-------+ : # * - is set automatically in the vr_config.c : register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(4), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_IA_CORE]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_GT_UNSLICED]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0 ,\ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_GT_SLICED]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" matches platform defaults -> could be dropped in another change
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 105: register "SerialIoDevMode" = "{ \ : [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ : [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ : [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ : [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ : [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ : [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ : }" these translate to zero, too
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 205: [4] = 0, \ : [5] = 0, \ : [6] = 0, \ : [7] = 0, \ zero -> drop
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
Patch Set 3: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 5: register "deep_sx_config" = "DSX_EN_WAKE_PIN"
when dsx is disabled, this one can be dropped, too; either in this change (because it's directly rel […]
I'd prefer to reason why this can be dropped in a separate change, and remove it from all mainboards where it's meaningless.
Hello build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49185
to look at the new patch set (#4).
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
mb/asrock/h110m: Remove zeroed options from devicetree
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Ic39b4c70ccb9ec21780c937322d63820064abbd1 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/49185/4
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 5: register "deep_sx_config" = "DSX_EN_WAKE_PIN"
I'd prefer to reason why this can be dropped in a separate change, and remove it from all mainboards […]
I agree. That should be done in a seperate change.
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 36: : # VR Settings Configuration : #+----------------+-------+-------+-------------+-------+ : #| Domain/Setting | SA | IA | GT Unsliced | GT | : #+----------------+-------+-------+-------------+-------+ : #| Psi1Threshold | 20A | 20A | 20A | 20A | : #| Psi2Threshold | 4A | 5A | 5A | 5A | : #| Psi3Threshold | 1A | 1A | 1A | 1A | : #| Psi3Enable | 1 | 1 | 1 | 1 | : #| Psi4Enable | 1 | 1 | 1 | 1 | : #| ImonSlope | 0 | 0 | 0 | 0 | : #| ImonOffset | 0 | 0 | 0 | 0 | : #| IccMax* | 0 | 0 | 0 | 0 | : #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | : #+----------------+-------+-------+-------------+-------+ : # * - is set automatically in the vr_config.c : register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(4), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_IA_CORE]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_GT_UNSLICED]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0 ,\ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_GT_SLICED]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }"
matches platform defaults -> could be dropped in another change
Done in CB:49188.
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 105: register "SerialIoDevMode" = "{ \ : [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ : [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ : [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ : [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ : [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ : [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ : }"
these translate to zero, too
Done
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 205: [4] = 0, \ : [5] = 0, \ : [6] = 0, \ : [7] = 0, \
zero -> drop
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
Patch Set 4: Code-Review+2
Hello build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49185
to look at the new patch set (#5).
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
mb/asrock/h110m: Remove zeroed options from devicetree
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Ic39b4c70ccb9ec21780c937322d63820064abbd1 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/49185/5
Attention is currently required from: Felix Singer. Hello build bot (Jenkins), Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49185
to look at the new patch set (#7).
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
mb/asrock/h110m: Remove zeroed options from devicetree
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Ic39b4c70ccb9ec21780c937322d63820064abbd1 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/49185/7
Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
Patch Set 8: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
mb/asrock/h110m: Remove zeroed options from devicetree
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Ic39b4c70ccb9ec21780c937322d63820064abbd1 Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/49185 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 25 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 909c050..77ff9ef 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -2,10 +2,6 @@
chip soc/intel/skylake
- register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_WAKE_PIN"
register "eist_enable" = "1" @@ -105,21 +101,6 @@ .voltage_limit = 1520 \ }"
- # PCH UART, SPI, I2C - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ - }" - # PL2 override 91W register "power_limits_config" = "{ .tdp_pl2_override = 91, @@ -138,7 +119,6 @@ device pci 01.0 on # PEG subsystemid 0x1849 0x1901 register "Peg0MaxLinkWidth" = "Peg0_x16" - register "SkipExtGfxScan" = "0"
# Configure PCIe clockgen in PCH register "PcieRpClkReqSupport[0]" = "1" @@ -210,10 +190,6 @@ [1] = 1, \ [2] = 1, \ [3] = 1, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ }" end device pci 19.0 off end # UART #2 @@ -380,7 +356,6 @@ device pci 1f.2 on end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaVcType" = "Vc1" - register "DspEnable" = "0" end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI