Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49185 )
Change subject: mb/asrock/h110m: Remove zeroed options from devicetree ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 5: register "deep_sx_config" = "DSX_EN_WAKE_PIN" when dsx is disabled, this one can be dropped, too; either in this change (because it's directly related. just mention it in the commit msg then) or in a separate change.
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 36: : # VR Settings Configuration : #+----------------+-------+-------+-------------+-------+ : #| Domain/Setting | SA | IA | GT Unsliced | GT | : #+----------------+-------+-------+-------------+-------+ : #| Psi1Threshold | 20A | 20A | 20A | 20A | : #| Psi2Threshold | 4A | 5A | 5A | 5A | : #| Psi3Threshold | 1A | 1A | 1A | 1A | : #| Psi3Enable | 1 | 1 | 1 | 1 | : #| Psi4Enable | 1 | 1 | 1 | 1 | : #| ImonSlope | 0 | 0 | 0 | 0 | : #| ImonOffset | 0 | 0 | 0 | 0 | : #| IccMax* | 0 | 0 | 0 | 0 | : #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | : #+----------------+-------+-------+-------------+-------+ : # * - is set automatically in the vr_config.c : register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(4), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_IA_CORE]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_GT_UNSLICED]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0 ,\ : .voltage_limit = 1520 \ : }" : : register "domain_vr_config[VR_GT_SLICED]" = "{ : .vr_config_enable = 1, \ : .psi1threshold = VR_CFG_AMP(20), \ : .psi2threshold = VR_CFG_AMP(5), \ : .psi3threshold = VR_CFG_AMP(1), \ : .psi3enable = 1, \ : .psi4enable = 1, \ : .imon_slope = 0x0, \ : .imon_offset = 0x0, \ : .icc_max = 0x0, \ : .voltage_limit = 1520 \ : }" matches platform defaults -> could be dropped in another change
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 105: register "SerialIoDevMode" = "{ \ : [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ : [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ : [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ : [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ : [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ : [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ : [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ : }" these translate to zero, too
https://review.coreboot.org/c/coreboot/+/49185/3/src/mainboard/asrock/h110m/... PS3, Line 205: [4] = 0, \ : [5] = 0, \ : [6] = 0, \ : [7] = 0, \ zero -> drop