Change in coreboot[master]: mb/intel: Add unaligned flag (%) sections that don't need alignment
Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37314 )
Change subject: mb/intel: Add unaligned flag (%) sections that don't need alignment ......................................................................
mb/intel: Add unaligned flag (%) sections that don't need alignment
Sections that won't be updated independently and don't need to be aligned.
Note: glkrvp/chromeos.fmd had unaligned RW_SECTION_{A,B} and is fixed now. leafhill/leafhill.8192.fmd had unaligned UNIFIED_MRC_CACHE and is fixed.
Change-Id: I9333dddd9ead3610216009fb6fd1ad6df5f05cf3 Signed-off-by: Hung-Te Lin hungte@chromium.org --- M src/mainboard/intel/baskingridge/chromeos.fmd M src/mainboard/intel/cannonlake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd M src/mainboard/intel/galileo/vboot.fmd M src/mainboard/intel/glkrvp/chromeos.fmd M src/mainboard/intel/icelake_rvp/chromeos.fmd M src/mainboard/intel/kblrvp/chromeos.fmd M src/mainboard/intel/kunimitsu/chromeos.fmd M src/mainboard/intel/leafhill/leafhill.16384.fmd M src/mainboard/intel/leafhill/leafhill.8192.fmd M src/mainboard/intel/minnow3/minnow3.fmd M src/mainboard/intel/strago/chromeos.fmd M src/mainboard/intel/wtm2/chromeos.fmd 14 files changed, 88 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37314/1
diff --git a/src/mainboard/intel/baskingridge/chromeos.fmd b/src/mainboard/intel/baskingridge/chromeos.fmd index 9852a22..a9675e6 100644 --- a/src/mainboard/intel/baskingridge/chromeos.fmd +++ b/src/mainboard/intel/baskingridge/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 } diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd index 39bd6c5..b2a8f70 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x380000 0xc80000 { RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x357fc0 + RW_FWID_A@0x367fc0% 0x40 } RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x357fc0 + RW_FWID_B@0x367fc0% 0x40 } RW_MISC@0x6d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -34,9 +34,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x280000 } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd index 39bd6c5..b2a8f70 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x380000 0xc80000 { RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x357fc0 - RW_FWID_A@0x367fc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x357fc0 + RW_FWID_A@0x367fc0% 0x40 } RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x357fc0 - RW_FWID_B@0x367fc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x357fc0 + RW_FWID_B@0x367fc0% 0x40 } RW_MISC@0x6d0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -34,9 +34,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x370000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x280000 } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd index 62e0f5d..0a7be5f 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x2bffc0 + RW_FWID_A@0x2cffc0% 0x40 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x2bffc0 + RW_FWID_B@0x2cffc0% 0x40 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -33,9 +33,9 @@ WP_RO@0x7d0000 0x430000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x33c000 } diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd index 4d349bd..d4f9021 100644 --- a/src/mainboard/intel/galileo/vboot.fmd +++ b/src/mainboard/intel/galileo/vboot.fmd @@ -20,13 +20,13 @@ SI_BIOS@0x200000 0x600000 { RW_SECTION_A@0x0 0xf0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0xdffc0 + RW_FWID_A@0xeffc0% 0x40 } RW_SECTION_B@0xf0000 0xf0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0xdffc0 + RW_FWID_B@0xeffc0% 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 RW_ELOG(PRESERVE)@0x1f0000 0x4000 @@ -40,11 +40,11 @@ RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 + RO_UNUSED@0x4000% 0xc000 RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0x7f000 COREBOOT(CBFS)@0x80000 0x170000 } diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd index 5d4ba46..fbaca9b 100644 --- a/src/mainboard/intel/glkrvp/chromeos.fmd +++ b/src/mainboard/intel/glkrvp/chromeos.fmd @@ -4,9 +4,9 @@ IFWI@0x1000 0x1ff000 RO_VPD(PRESERVE)@0x200000 0x4000 RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 COREBOOT(CBFS)@0x1000 0x1ab000 GBB@0x1ac000 0x40000 RO_UNUSED@0x1ec000 0x10000 @@ -27,17 +27,17 @@ FPF_STATUS@0x3B000 0x1000 TMP_UNUSED_HOLE@0x3C000 0xE000 } - RW_SECTION_A@0x44a000 0x477800 { + RW_SECTION_A@0x44a000 0x478000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x4677c0 - RW_FWID_A@0x4777c0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x467fc0 + RW_FWID_A@0x477fc0% 0x40 } - RW_SECTION_B@0x8c1800 0x477800 { + RW_SECTION_B@0x8c2000 0x478000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x4677c0 - RW_FWID_B@0x4777c0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x467fc0 + RW_FWID_B@0x477fc0% 0x40 } - RW_NVRAM(PRESERVE)@0xd39000 0x6000 + RW_NVRAM(PRESERVE)@0xd3a000 0x6000 SMMSTORE(PRESERVE)@0xd40000 0x40000 RW_LEGACY(CBFS)@0xd80000 0x1b0000 BIOS_UNUSABLE@0xf3f000 0x40000 diff --git a/src/mainboard/intel/icelake_rvp/chromeos.fmd b/src/mainboard/intel/icelake_rvp/chromeos.fmd index f4db8b4..037de53 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/icelake_rvp/chromeos.fmd @@ -7,13 +7,13 @@ SI_BIOS@0x400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x2bffc0 + RW_FWID_A@0x2cffc0% 0x40 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x2bffc0 + RW_FWID_B@0x2cffc0% 0x40 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { @@ -33,9 +33,9 @@ WP_RO@0x7d0000 0x430000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x33c000 } diff --git a/src/mainboard/intel/kblrvp/chromeos.fmd b/src/mainboard/intel/kblrvp/chromeos.fmd index 9ba1bf7..6be2a40 100644 --- a/src/mainboard/intel/kblrvp/chromeos.fmd +++ b/src/mainboard/intel/kblrvp/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0xe00000 { RW_SECTION_A@0x0 0x3f0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x3dffc0 + RW_FWID_A@0x3effc0% 0x40 } RW_SECTION_B@0x3f0000 0x3f0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x3dffc0 + RW_FWID_B@0x3effc0% 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 RW_ELOG(PRESERVE)@0x7f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x300000 } diff --git a/src/mainboard/intel/kunimitsu/chromeos.fmd b/src/mainboard/intel/kunimitsu/chromeos.fmd index 9ba1bf7..6be2a40 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.fmd +++ b/src/mainboard/intel/kunimitsu/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0xe00000 { RW_SECTION_A@0x0 0x3f0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x3dffc0 + RW_FWID_A@0x3effc0% 0x40 } RW_SECTION_B@0x3f0000 0x3f0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x3dffc0 + RW_FWID_B@0x3effc0% 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 RW_ELOG(PRESERVE)@0x7f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0xef000 COREBOOT(CBFS)@0xf0000 0x300000 } diff --git a/src/mainboard/intel/leafhill/leafhill.16384.fmd b/src/mainboard/intel/leafhill/leafhill.16384.fmd index a91ba9a..a7a6b26 100644 --- a/src/mainboard/intel/leafhill/leafhill.16384.fmd +++ b/src/mainboard/intel/leafhill/leafhill.16384.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x2ff000 - FMAP@0x300000 0x800 - COREBOOT(CBFS)@0x300800 0xc1d800 + FMAP@0x300000% 0x800 + COREBOOT(CBFS)@0x300800% 0xc1d800 UNIFIED_MRC_CACHE@0xf1e000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 diff --git a/src/mainboard/intel/leafhill/leafhill.8192.fmd b/src/mainboard/intel/leafhill/leafhill.8192.fmd index 3f4d21b..3fe71e0 100644 --- a/src/mainboard/intel/leafhill/leafhill.8192.fmd +++ b/src/mainboard/intel/leafhill/leafhill.8192.fmd @@ -1,9 +1,9 @@ FLASH 8M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x321000 0x800 - COREBOOT(CBFS)@0x321800 0x300000 - UNIFIED_MRC_CACHE@0x621800 0x21000 { + FMAP@0x321000% 0x800 + COREBOOT(CBFS)@0x321800% 0x300800 + UNIFIED_MRC_CACHE@0x622000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd index d51b5ee..9733567 100644 --- a/src/mainboard/intel/minnow3/minnow3.fmd +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -1,8 +1,8 @@ FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 - FMAP@0x301000 0x800 - COREBOOT(CBFS)@0x301800 0x3dc800 + FMAP@0x301000% 0x800 + COREBOOT(CBFS)@0x301800% 0x3dc800 UNIFIED_MRC_CACHE@0x6de000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 diff --git a/src/mainboard/intel/strago/chromeos.fmd b/src/mainboard/intel/strago/chromeos.fmd index 923c8ee..5dec9ec 100644 --- a/src/mainboard/intel/strago/chromeos.fmd +++ b/src/mainboard/intel/strago/chromeos.fmd @@ -6,13 +6,13 @@ SI_BIOS@0x200000 0x600000 { RW_SECTION_A@0x0 0xf0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0xdffc0 + RW_FWID_A@0xeffc0% 0x40 } RW_SECTION_B@0xf0000 0xf0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0xdffc0 + RW_FWID_B@0xeffc0% 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 RW_ELOG(PRESERVE)@0x1f0000 0x4000 @@ -28,9 +28,9 @@ RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_FRID_PAD@0x840% 0x7c0 GBB@0x1000 0x6f000 COREBOOT(CBFS)@0x70000 0x180000 } diff --git a/src/mainboard/intel/wtm2/chromeos.fmd b/src/mainboard/intel/wtm2/chromeos.fmd index 9852a22..a9675e6 100644 --- a/src/mainboard/intel/wtm2/chromeos.fmd +++ b/src/mainboard/intel/wtm2/chromeos.fmd @@ -13,23 +13,23 @@ } RW_SECTION_A@0x80000 0x100000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x7ffc0 - RW_FWID_A@0x8ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000% 0x7ffc0 + RW_FWID_A@0x8ffc0% 0x40 RW_UNUSED_A@0x90000 0x70000 } RW_SECTION_B@0x180000 0x100000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x7ffc0 - RW_FWID_B@0x8ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000% 0x7ffc0 + RW_FWID_B@0x8ffc0% 0x40 RW_UNUSED_B@0x90000 0x70000 } RO_UNUSED_1@0x280000 0x170000 RO_VPD(PRESERVE)@0x3f0000 0x20000 RO_UNUSED_2@0x410000 0xe0000 RO_SECTION@0x4f0000 0x190000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0xf7c0 + FMAP@0x0% 0x800 + RO_FRID@0x800% 0x40 + RO_PADDING@0x840% 0xf7c0 GBB@0x10000 0x80000 COREBOOT(CBFS)@0x90000 0x100000 }
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37314 )
Change subject: mb/intel: Add unaligned flag (%) sections that don't need alignment ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37314 )
Change subject: mb/intel: Add unaligned flag (%) sections that don't need alignment ......................................................................
Patch Set 2: Code-Review+2
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37314 )
Change subject: mb/intel: Add unaligned flag (%) sections that don't need alignment ......................................................................
Patch Set 2: Code-Review-1
set to -1 since the alignment hasn't reached an conclusion.
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37314?usp=email )
Change subject: mb/intel: Add unaligned flag (%) sections that don't need alignment ......................................................................
Abandoned
-
Furquan Shaikh (Code Review) -
Hung-Te Lin (Code Review)
-
Julius Werner (Code Review)
-
Stefan Reinauer (Code Review)