Change in ...coreboot[master]: soc/amd/stoneyridge: Add generic PM1 register clear function

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31159

Change subject: soc/amd/stoneyridge: Add generic PM1 register clear function
......................................................................

soc/amd/stoneyridge: Add generic PM1 register clear function

Convert vboot_platform_prepare_reboot() to call a function in
soc//stoneyridge.  A subsequent patch will add another call to
the new function, and this change removes any inference of a
dependency on vboot.

BUG=b:122725586

Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/pmutil.c
2 files changed, 14 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31159/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 1652bbc..3ae6b4a 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -604,4 +604,10 @@
 /* Initialize all the i2c buses that are not marked with early init. */
 void i2c_soc_init(void);

+/*
+ * If a system reset is about to be requested, modify the PM1 register so it
+ * will never be misinterpreted as an S3 resume.
+ */
+void set_pm1cnt_s5(void);
+
 #endif /* __STONEYRIDGE_H__ */
diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c
index d2b3ac7..bfb5f42 100644
--- a/src/soc/amd/stoneyridge/pmutil.c
+++ b/src/soc/amd/stoneyridge/pmutil.c
@@ -34,9 +34,9 @@
    return acpi_sleep_from_pm1(pm_cnt) == ACPI_S3;
 }

-/* If vboot requests a system reset, modify the PM1 register so it will never be
- * misinterpreted as an S3 resume. */
-void vboot_platform_prepare_reboot(void)
+/* If a system reset is about to be requested, modify the PM1 register so it
+ * will never be misinterpreted as an S3 resume. */
+void set_pm1cnt_s5(void)
 {
    uint16_t pm1;

@@ -45,3 +45,8 @@
    pm1 |= SLP_TYP_S5 << SLP_TYP_SHIFT;
    acpi_write16(MMIO_ACPI_PM1_CNT_BLK, pm1);
 }
+
+void vboot_platform_prepare_reboot(void)
+{
+	set_pm1cnt_s5();
+}

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31159 )

Change subject: soc/amd/stoneyridge: Add generic PM1 register clear function
......................................................................

Patch Set 1: Code-Review+2

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31159 )

Change subject: soc/amd/stoneyridge: Add generic PM1 register clear function
......................................................................

Patch Set 1: Code-Review+1

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31159 )

Change subject: soc/amd/stoneyridge: Add generic PM1 register clear function
......................................................................

soc/amd/stoneyridge: Add generic PM1 register clear function

Convert vboot_platform_prepare_reboot() to call a function in
soc//stoneyridge.  A subsequent patch will add another call to
the new function, and this change removes any inference of a
dependency on vboot.

BUG=b:122725586

Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8
Signed-off-by: Marshall Dawson 
Reviewed-on: https://review.coreboot.org/c/31159
Tested-by: build bot (Jenkins) 
Reviewed-by: Martin Roth 
Reviewed-by: Paul Menzel 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/pmutil.c
2 files changed, 14 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Martin Roth: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 1652bbc..3ae6b4a 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -604,4 +604,10 @@
 /* Initialize all the i2c buses that are not marked with early init. */
 void i2c_soc_init(void);

+/*
+ * If a system reset is about to be requested, modify the PM1 register so it
+ * will never be misinterpreted as an S3 resume.
+ */
+void set_pm1cnt_s5(void);
+
 #endif /* __STONEYRIDGE_H__ */
diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c
index d2b3ac7..bfb5f42 100644
--- a/src/soc/amd/stoneyridge/pmutil.c
+++ b/src/soc/amd/stoneyridge/pmutil.c
@@ -34,9 +34,9 @@
    return acpi_sleep_from_pm1(pm_cnt) == ACPI_S3;
 }

-/* If vboot requests a system reset, modify the PM1 register so it will never be
- * misinterpreted as an S3 resume. */
-void vboot_platform_prepare_reboot(void)
+/* If a system reset is about to be requested, modify the PM1 register so it
+ * will never be misinterpreted as an S3 resume. */
+void set_pm1cnt_s5(void)
 {
    uint16_t pm1;

@@ -45,3 +45,8 @@
    pm1 |= SLP_TYP_S5 << SLP_TYP_SHIFT;
    acpi_write16(MMIO_ACPI_PM1_CNT_BLK, pm1);
 }
+
+void vboot_platform_prepare_reboot(void)
+{
+	set_pm1cnt_s5();
+}