Change in coreboot[master]: soc/intel/alderlake: mb/intel/sm: Add tcss code - coreboot-gerrit

10 May 2021


      Attention is currently required from: Maulik V Vaghela.
Deepti Deshatty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54005 )
Change subject: soc/intel/alderlake: mb/intel/sm: Add tcss code
......................................................................
Patch Set 1:
This change is ready for review.
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/54005
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I36bf5ba7eb4b633c6e5c61fbc94b5b457ffb93d9
Gerrit-Change-Number: 54005
Gerrit-PatchSet: 1
Gerrit-Owner: Deepti Deshatty deepti.deshatty@intel.com
Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Attention: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Comment-Date: Mon, 10 May 2021 01:38:29 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment