Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31724
Change subject: mb/google/hatch: Initialize all gpios ......................................................................
mb/google/hatch: Initialize all gpios
BUG=b:123490912 BRANCH=None TEST=flash BIOS and make sure hatch boots up properly
Change-Id: I9e41f0b38703f2c7a2b5a7ac9b108f8f10070004 Signed-off-by: Shelley Chen shchen@google.com --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 296 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/31724/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 857204e..81a1a03 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -19,182 +19,391 @@ #include <commonlib/helpers.h>
static const struct pad_config gpio_table[] = { - /* SD_1P8_SEL => NC */ + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A0, NONE, DEEP, LEVEL, NONE), + /* A1 : ESPI_IO0 */ + /* A2 : ESPI_IO1 */ + /* A3 : ESPI_IO2 */ + /* A4 : ESPI_IO3 */ + /* A5 : ESPI_CS# */ + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A6, NONE, DEEP, LEVEL, NONE), + /* A7 : PP3300_SOC_A */ + PAD_CFG_GPI(GPP_A7, NONE, PLTRST), + /* A8 : EMR_GARAGE_DET ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A9 : ESPI_CLK */ + /* A10 : PEN_RESET_ODL */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : SUSWARN_L */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : ESPI_RST_L */ + /* A15 : SUSACK_L */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : SD_1P8_SEL => NC */ PAD_NC(GPP_A16, DN_20K), - /* EN_PP3300_SD_DX */ + /* A17 : EN_PP3300_SD_DX */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), - /* EN_PP3300_WWAN */ + /* A18 : EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* WWAN_RADIO_DISABLE_1V8_ODL */ + /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */ PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* A20 : M2_INT_L */ + PAD_CFG_GPI_APIC(GPP_A20, NONE, DEEP, LEVEL, NONE), /* - * TRACKPAD_INT_ODL (wake) + * A21 : TRACKPAD_INT_ODL (wake) * TODO Combine into single gpio, when ITSS IPCx configuration * is fixed in FSP. */ PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), - /* SRCCLKREQ1 */ + /* A22 : FPMCU_PCH_BOOT0 */ + PAD_CFG_GPO(GPP_A22, 0, DEEP), + /* A23 : FPMCU_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, NONE), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : GPP_B2 ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : GPP_B3 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : GPP_B4 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : GPP_B5 ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : SRCCLKREQ1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* PCIE_14_WLAN_CLKREQ_ODL */ + /* B7 : GPP_B7 ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : PCIE_14_WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_CS_L */ + /* B9 : GPP_B9 ==> NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : GPP_B10 ==> NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* B12 : SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : GPP_B14_STRAP */ + PAD_CFG_GPI(GPP_B14, NONE, PLTRST), + /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_CLK */ + /* B16 : H1_SLAVE_SPI_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MISO_R */ + /* B17 : H1_SLAVE_SPI_MISO_R */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MOSI_R */ + /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* GPP_C0 => NC */ + /* B19 : GPP_B19 ==> NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : PCH_SPI_FPMCU_CLK_R */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : PCH_SPI_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : PCH_SPI_FPMCU_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* B23 : GPP_B23_STRAP */ + PAD_CFG_GPI(GPP_B23, NONE, PLTRST), + + /* C0 : GPP_C0 => NC */ PAD_NC(GPP_C0, NONE), - /* PCIE_14_WLAN_WAKE_ODL */ + /* C1 : PCIE_14_WLAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C1, NONE, DEEP, EDGE_SINGLE), - /* GPP_C2 => NC */ + /* C2 : GPP_C2 => NC */ PAD_NC(GPP_C2, NONE), - /* WLAN_OFF_L */ + /* C3 : WLAN_OFF_L */ PAD_CFG_GPO(GPP_C3, 1, DEEP), - /* TOUCHSCREEN_DIS_L */ + /* C4 : TOUCHSCREEN_DIS_L */ PAD_CFG_GPO(GPP_C4, 1, DEEP), - /* GPP_C5 => NC */ + /* C5 : GPP_C5 => NC */ PAD_NC(GPP_C5, NONE), - /* PEN_PDCT_OD_L */ + /* C6 : PEN_PDCT_OD_L */ PAD_CFG_GPI(GPP_C6, NONE, DEEP), - /* PEN_IRQ_OD_L */ + /* C7 : PEN_IRQ_OD_L */ PAD_CFG_GPI_APIC(GPP_C7, NONE, DEEP, LEVEL, NONE), - /* GPP_C10_TP */ + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : GPP_10 ==> GPP_C10_TP */ PAD_NC(GPP_C10, DN_20K), - /* GPP_C11_TP */ + /* C11 : GPP_11 ==> GPP_C11_TP */ PAD_NC(GPP_C11, DN_20K), - /* BT_DISABLE_L */ + /* C12 : GPP_C12 ==> NC */ + PAD_NC(GPP_C12, NONE), + /* C13 : EC_PCH_INT_L + * TODO Configure it back to invert mode, when + * ITSS IPCx configuration is fixed in FSP. + */ + PAD_CFG_GPI_APIC(GPP_C13, NONE, DEEP, LEVEL, NONE), + /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 1, DEEP), - /* WWAN_DPR_SAR_ODL + /* C15 : WWAN_DPR_SAR_ODL * * TODO: Driver doesn't use this pin as of now. In case driver starts * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* PCH_I2C_TRACKPAD_SDA */ + /* C16 : PCH_I2C_TRACKPAD_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* PCH_I2C_TRACKPAD_SCL */ + /* C17 : PCH_I2C_TRACKPAD_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* PCH_I2C_TOUCHSCREEN_SDA */ + /* C18 : PCH_I2C_TOUCHSCREEN_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* PCH_I2C_TOUCHSCREEN_SCL */ + /* C19 : PCH_I2C_TOUCHSCREEN_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* PCH_WP_OD */ + /* C20 : PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* - * H1_PCH_INT_ODL + * C21 : H1_PCH_INT_ODL * TODO Configure it back to invert mode, when * ITSS IPCx configuration is fixed in FSP. */ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE), - /* EC_IN_RW_OD */ + /* C22 : EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* WLAN_PE_RST# */ + /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* WWAN_CONFIG_0 */ + + /* D0 : TP31 */ + PAD_NC(GPP_D0, NONE), + /* D1 : TP16 */ + PAD_NC(GPP_D1, NONE), + /* D2 : TP26 */ + PAD_NC(GPP_D2, NONE), + /* D3 : TP27 */ + PAD_NC(GPP_D3, NONE), + /* D4 : TP40 */ + PAD_NC(GPP_D4, NONE), + /* D5 : WWAN_CONFIG_0 */ PAD_NC(GPP_D5, NONE), - /* WWAN_CONFIG_1 */ + /* D6 : WWAN_CONFIG_1 */ PAD_NC(GPP_D6, NONE), - /* WWAN_CONFIG_2 */ + /* D7 : WWAN_CONFIG_2 */ PAD_NC(GPP_D7, NONE), - /* WWAN_CONFIG_3 */ + /* D8 : WWAN_CONFIG_3 */ PAD_NC(GPP_D8, NONE), - /* TOUCHSCREEN_RST_L */ + /* D9 : GPP_D9 ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : GPP_D10 ==> NC */ + PAD_NC(GPP_D10, NONE), + /* D11 : GPP_D11 ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D12 : GPP_D12 */ + PAD_CFG_GPI(GPP_D12, NONE, DEEP), + /* D13 : ISH_UART_RX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART_TX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* - * TOUCHSCREEN_INT_L + * D16 : TOUCHSCREEN_INT_L * TODO Configure it back to invert mode, when * ITSS IPCx configuration is fixed in FSP. */ PAD_CFG_GPI_APIC(GPP_D16, NONE, DEEP, LEVEL, NONE), + /* D17 : PCH_HP_SDW_CLK */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), + /* D18 : PCH_HP_SDW_DAT */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2), + /* D19 : DMIC_CLK_0_SNDW4_CLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* D20 : DMIC_DATA_0_SNDW4_DATA */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* - * TRACKPAD_INT_ODL + * D21 : TRACKPAD_INT_ODL * TODO Combine into single gpio with invert mode, when ITSS * IPCx configuration is fixed in FSP. */ PAD_CFG_GPI_APIC(GPP_D21, NONE, PLTRST, LEVEL, NONE), - /* SATAGP1 */ + /* D22 : GPP_D22 ==> NC */ + PAD_NC(GPP_D22, NONE), + /* D23 : SPP_MCLK */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E0 : GPP_E0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E1 : SATAGP1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), - /* M2_SSD_PE_WAKE_ODL */ + /* E2 : GPP_E2 ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E3 : GPP_E3 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : M2_SSD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_E4, NONE, DEEP), - /* SATA_DEVSLP1 */ + /* E5 : SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), - /* USB_C_OC_OD USB_OC2*/ + /* E6 : M2_SSD_RST_L */ + PAD_CFG_GPO(GPP_E6, 1, DEEP), + /* E7 : GPP_E7 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E8 : GPP_E8 ==> NC */ + PAD_NC(GPP_E8, NONE), + /* E9 : GPP_E9 ==> NC */ + PAD_NC(GPP_E9, NONE), + /* E10 : GPP_E10 ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : USB_C_OC_OD USB_OC2*/ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), - /* USB_A_OC_OD USB_OC3*/ + /* E12 : USB_A_OC_OD USB_OC3*/ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - /* USB_C0_DP_HPD */ + /* E13 : USB_C0_DP_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), - /* DDI2_HPD_ODL */ + /* E14 : DDI2_HPD_ODL */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* DDPD_HPD2 => NC */ + /* E15 : DDPD_HPD2 => NC */ PAD_NC(GPP_E15, DN_20K), - /* DDPE_HPD2 => NC */ + /* E16 : DDPE_HPD2 => NC */ PAD_NC(GPP_E16, DN_20K), - /* EDP_HPD */ + /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), - /* DDPB_CTRLCLK => NC */ + /* E18 : DDPB_CTRLCLK => NC */ PAD_NC(GPP_E18, DN_20K), - /* DDPC_CTRLCLK => NC */ + /* E19 : GPP_E19_STRAP */ + PAD_CFG_GPI(GPP_E19, NONE, DEEP), + /* E20 : DDPC_CTRLCLK => NC */ PAD_NC(GPP_E20, DN_20K), - /* DDPD_CTRLCLK => NC */ + /* E21 : GPP_E21_STRAP */ + PAD_CFG_GPI(GPP_E21, NONE, DEEP), + /* E22 : DDPD_CTRLCLK => NC */ PAD_NC(GPP_E22, DN_20K), - /* GPIO_WWAN_WLAN_COEX3 */ + /* E23 : GPP_E23_STRAP */ + PAD_CFG_GPI(GPP_E23, NONE, DEEP), + + /* F0 : GPIO_WWAN_WLAN_COEX3 */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), - /* WWAN_RESET_1V8_ODL */ + /* F1 : WWAN_RESET_1V8_ODL */ PAD_CFG_GPO(GPP_F1, 1, DEEP), - /* UART_WWANTX_WLANRX_COEX1 */ + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), + /* F3 : GPP_F3 ==> NC */ + PAD_NC(GPP_F3, NONE), + /* F4 : CNV_BRI_DT */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), + /* F6 : CNV_RGI_DT */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + /* F8 : UART_WWANTX_WLANRX_COEX1 */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), - /* UART_WWANRX_WLANTX_COEX2 */ + /* F9 : UART_WWANRX_WLANTX_COEX2 */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), - /* PCH_MEM_STRAP0 */ - PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* PCH_MEM_STRAP1 */ - PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* PCH_MEM_STRAP2 */ + /* F10 : GPP_F10 ==> NC */ + PAD_NC(GPP_F10, NONE), + /* F11 : PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_F11, NONE, PLTRST), - /* PCH_MEM_STRAP3 */ + /* F12 : GPP_F12 ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GPP_F13 ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GPP_F14 ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GPP_F15 ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GPP_F16 ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : GPP_F17 ==> NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : GPP_F18 ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : GPP_F19 ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_F22, NONE, PLTRST), - /* SD_CMD */ + /* F23 : GPP_F23 ==> NC */ + PAD_NC(GPP_F23, NONE), + + /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), - /* SD_DATA0 */ + /* G1 : SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), - /* SD_DATA1 */ + /* G2 : SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), - /* SD_DATA2 */ + /* G3 : SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), - /* SD_DATA3 */ + /* G4 : SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), - /* SD_CD# */ + /* G5 : SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), - /* SD_CLK */ + /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), - /* SD_WP => NC */ + /* G7 : SD_WP => NC */ PAD_NC(GPP_G7, DN_20K),
- /* PCH_I2C_PEN_SDA */ + /* + * H0 : AUDIO IRQ + * TODO Configure it back to invert mode, when + * ITSS IPCx configuration is fixed in FSP. + */ + PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, NONE), + /* H1 : CNV_RF_RESET_L */ + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), + /* H2 : CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), + /* H3 : SPEAKER SD MODE ENABLE */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H4 : PCH_I2C_PEN_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* PCH_I2C_PEN_SCL */ + /* H5 : PCH_I2C_PEN_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* PCH_I2C_SAR0_MST_SDA */ + /* H6 : PCH_I2C_SAR0_MST_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* PCH_I2C_SAR0_MST_SCL */ + /* H7 : PCH_I2C_SAR0_MST_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* PCH_I2C_M2_AUDIO_SAR1_SDA */ + /* H8 : PCH_I2C_M2_AUDIO_SAR1_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - /* PCH_I2C_M2_AUDIO_SAR1_SCL */ + /* H9 : PCH_I2C_M2_AUDIO_SAR1_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), - /* PCH_I2C_TRACKPAD_SDA */ + /* H10 : PCH_I2C_TRACKPAD_SDA */ PAD_NC(GPP_H10, NONE), - /* PCH_I2C_TRACKPAD_SCL */ + /* H11 : PCH_I2C_TRACKPAD_SCL */ PAD_NC(GPP_H11, NONE), - /* SD card detect VGPIO */ - PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP), + /* H12 : GPP_H12 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : GPP_H13 ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H14 : GPP_H14 ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : GPP_H15 ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : GPP_H16 ==> NC */ + PAD_NC(GPP_H16, NONE), + /* H17 : TP1 */ + PAD_NC(GPP_H17, NONE), + /* H18 : CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : GPP_H19 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : TP41 */ + PAD_NC(GPP_H20, NONE), + /* H21 : XTAL_FREQ_SEL */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : GPP_H22 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : GPP_H23_STRAP */ + PAD_CFG_GPI(GPP_H23, NONE, DEEP),
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + + /* SD card detect VGPIO */ + PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP), };
const struct pad_config *__weak variant_gpio_table(size_t *num) @@ -205,24 +414,26 @@
/* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { - /* H1_SLAVE_SPI_CS_L */ + /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_CLK */ + /* B16 : H1_SLAVE_SPI_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MISO_R */ + /* B17 : H1_SLAVE_SPI_MISO_R */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MOSI_R */ + /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* - * H1_PCH_INT_ODL + * C21 : H1_PCH_INT_ODL * TODO Configure it back to invert mode, when * ITSS IPCx configuration is fixed in FSP. */ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE), - /* WLAN_PE_RST# */ + /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), };
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31724 )
Change subject: mb/google/hatch: Initialize all gpios ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/#/c/31724/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31724/1//COMMIT_MSG@7 PS1, Line 7: gpios GPIOs
https://review.coreboot.org/#/c/31724/1//COMMIT_MSG@8 PS1, Line 8: Please elaborate what values they are initialized to.
https://review.coreboot.org/#/c/31724/1//COMMIT_MSG@11 PS1, Line 11: BIOS firmware
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31724 )
Change subject: mb/google/hatch: Initialize all gpios ......................................................................
Patch Set 2:
(34 comments)
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/gpio.c:
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 31: /* A7 : PP3300_SOC_A */ : PAD_CFG_GPI(GPP_A7, NONE, PLTRST), This is just PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 37: PAD_CFG_GPO(GPP_A10, 0, DEEP), This should be PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 48: DN_20K I think we should get rid of this.
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 65: FPMCU_PCH_INT_ODL Not for this change, but if this is being treated as a wake source, we will have to enable that on the same line.
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 97: GPP_B14 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 115: GPP_B23 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 130: GPP_C6 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 132: GPP_C7 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 202: GPP_D12 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 203: /* D13 : ISH_UART_RX */ : PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), : /* D14 : ISH_UART_TX */ : PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 210: TOUCHSCREEN_INT_L Net name needs to be updated.
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 211: TODO Configure it back to invert mode, when : * ITSS IPCx configuration is fixed in FSP. This is actually not true.
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 216: GPP_D17 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 218: GPP_D18 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 220: PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 222: GPP_D20 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 247: GPP_E6 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 256: * space before *
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 258: * same here
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 265: DN_20K NONE
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 267: DN_20K NONE
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 271: DN_20K NONE
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 273: GPP_E19 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 275: DN_20K NONE
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 277: GPP_E21 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 279: DN_20K NONE
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 281: GPP_E23 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 288: DN_20K Not required
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 362: GPP_H4 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 364: GPP_H5 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 396: GPP_H21 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 400: GPP_H23 PAD_NC
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 402: GPD2 We should check if other GPDs need to be configured too.
https://review.coreboot.org/#/c/31724/2/src/mainboard/google/hatch/variants/... PS2, Line 436: DN_20K NONE. Why is this configured early and not the rest of MEM config GPIOs?
Hello build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31724
to look at the new patch set (#3).
Change subject: mb/google/hatch: Initialize all gpios ......................................................................
mb/google/hatch: Initialize all gpios
BUG=b:123490912 BRANCH=None TEST=flash BIOS and make sure hatch boots up properly
Change-Id: I9e41f0b38703f2c7a2b5a7ac9b108f8f10070004 Signed-off-by: Shelley Chen shchen@google.com --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 315 insertions(+), 99 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/31724/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31724 )
Change subject: mb/google/hatch: Initialize all gpios ......................................................................
Patch Set 3: Code-Review+2
Shelley Chen has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31724 )
Change subject: mb/google/hatch: Initialize all gpios ......................................................................
mb/google/hatch: Initialize all gpios
BUG=b:123490912 BRANCH=None TEST=flash BIOS and make sure hatch boots up properly
Change-Id: I9e41f0b38703f2c7a2b5a7ac9b108f8f10070004 Signed-off-by: Shelley Chen shchen@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31724 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 315 insertions(+), 99 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 857204e..35dd912 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -19,182 +19,387 @@ #include <commonlib/helpers.h>
static const struct pad_config gpio_table[] = { - /* SD_1P8_SEL => NC */ - PAD_NC(GPP_A16, DN_20K), - /* EN_PP3300_SD_DX */ + /* A0 : SAR0_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A0, NONE, DEEP, LEVEL, NONE), + /* A1 : ESPI_IO0 */ + /* A2 : ESPI_IO1 */ + /* A3 : ESPI_IO2 */ + /* A4 : ESPI_IO3 */ + /* A5 : ESPI_CS# */ + /* A6 : SAR1_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A6, NONE, DEEP, LEVEL, NONE), + /* A7 : PP3300_SOC_A */ + PAD_NC(GPP_A7, NONE), + /* A8 : EMR_GARAGE_DET ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A9 : ESPI_CLK */ + /* A10 : PEN_RESET_ODL */ + PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : SUSWARN_L */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : ESPI_RST_L */ + /* A15 : SUSACK_L */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : SD_1P8_SEL => NC */ + PAD_NC(GPP_A16, NONE), + /* A17 : EN_PP3300_SD_DX */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), - /* EN_PP3300_WWAN */ + /* A18 : EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_A18, 1, DEEP), - /* WWAN_RADIO_DISABLE_1V8_ODL */ + /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */ PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* A20 : M2_INT_L */ + PAD_CFG_GPI_APIC(GPP_A20, NONE, DEEP, LEVEL, NONE), /* - * TRACKPAD_INT_ODL (wake) + * A21 : TRACKPAD_INT_ODL (wake) * TODO Combine into single gpio, when ITSS IPCx configuration * is fixed in FSP. */ PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), - /* SRCCLKREQ1 */ + /* A22 : FPMCU_PCH_BOOT0 */ + PAD_CFG_GPO(GPP_A22, 0, DEEP), + /* A23 : FPMCU_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, NONE), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : GPP_B2 ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : GPP_B3 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : GPP_B4 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : GPP_B5 ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : SRCCLKREQ1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* PCIE_14_WLAN_CLKREQ_ODL */ + /* B7 : GPP_B7 ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : PCIE_14_WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_CS_L */ + /* B9 : GPP_B9 ==> NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : GPP_B10 ==> NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* B12 : SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_CLK */ + /* B16 : H1_SLAVE_SPI_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MISO_R */ + /* B17 : H1_SLAVE_SPI_MISO_R */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MOSI_R */ + /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* GPP_C0 => NC */ + /* B19 : GPP_B19 ==> NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : PCH_SPI_FPMCU_CLK_R */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : PCH_SPI_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : PCH_SPI_FPMCU_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* B23 : GPP_B23_STRAP */ + PAD_NC(GPP_B23, NONE), + + /* C0 : GPP_C0 => NC */ PAD_NC(GPP_C0, NONE), - /* PCIE_14_WLAN_WAKE_ODL */ + /* C1 : PCIE_14_WLAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C1, NONE, DEEP, EDGE_SINGLE), - /* GPP_C2 => NC */ + /* C2 : GPP_C2 => NC */ PAD_NC(GPP_C2, NONE), - /* WLAN_OFF_L */ + /* C3 : WLAN_OFF_L */ PAD_CFG_GPO(GPP_C3, 1, DEEP), - /* TOUCHSCREEN_DIS_L */ + /* C4 : TOUCHSCREEN_DIS_L */ PAD_CFG_GPO(GPP_C4, 1, DEEP), - /* GPP_C5 => NC */ + /* C5 : GPP_C5 => NC */ PAD_NC(GPP_C5, NONE), - /* PEN_PDCT_OD_L */ - PAD_CFG_GPI(GPP_C6, NONE, DEEP), - /* PEN_IRQ_OD_L */ - PAD_CFG_GPI_APIC(GPP_C7, NONE, DEEP, LEVEL, NONE), - /* GPP_C10_TP */ + /* C6 : PEN_PDCT_OD_L */ + PAD_NC(GPP_C6, NONE), + /* C7 : PEN_IRQ_OD_L */ + PAD_NC(GPP_C7, NONE), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : GPP_10 ==> GPP_C10_TP */ PAD_NC(GPP_C10, DN_20K), - /* GPP_C11_TP */ + /* C11 : GPP_11 ==> GPP_C11_TP */ PAD_NC(GPP_C11, DN_20K), - /* BT_DISABLE_L */ + /* C12 : GPP_C12 ==> NC */ + PAD_NC(GPP_C12, NONE), + /* C13 : EC_PCH_INT_L + * TODO Configure it back to invert mode, when + * ITSS IPCx configuration is fixed in FSP. + */ + PAD_CFG_GPI_APIC(GPP_C13, NONE, DEEP, LEVEL, NONE), + /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 1, DEEP), - /* WWAN_DPR_SAR_ODL + /* C15 : WWAN_DPR_SAR_ODL * * TODO: Driver doesn't use this pin as of now. In case driver starts * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* PCH_I2C_TRACKPAD_SDA */ + /* C16 : PCH_I2C_TRACKPAD_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* PCH_I2C_TRACKPAD_SCL */ + /* C17 : PCH_I2C_TRACKPAD_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* PCH_I2C_TOUCHSCREEN_SDA */ + /* C18 : PCH_I2C_TOUCHSCREEN_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* PCH_I2C_TOUCHSCREEN_SCL */ + /* C19 : PCH_I2C_TOUCHSCREEN_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* PCH_WP_OD */ + /* C20 : PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* - * H1_PCH_INT_ODL + * C21 : H1_PCH_INT_ODL * TODO Configure it back to invert mode, when * ITSS IPCx configuration is fixed in FSP. */ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE), - /* EC_IN_RW_OD */ + /* C22 : EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), - /* WLAN_PE_RST# */ + /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* WWAN_CONFIG_0 */ + + /* D0 : TP31 */ + PAD_NC(GPP_D0, NONE), + /* D1 : TP16 */ + PAD_NC(GPP_D1, NONE), + /* D2 : TP26 */ + PAD_NC(GPP_D2, NONE), + /* D3 : TP27 */ + PAD_NC(GPP_D3, NONE), + /* D4 : TP40 */ + PAD_NC(GPP_D4, NONE), + /* D5 : WWAN_CONFIG_0 */ PAD_NC(GPP_D5, NONE), - /* WWAN_CONFIG_1 */ + /* D6 : WWAN_CONFIG_1 */ PAD_NC(GPP_D6, NONE), - /* WWAN_CONFIG_2 */ + /* D7 : WWAN_CONFIG_2 */ PAD_NC(GPP_D7, NONE), - /* WWAN_CONFIG_3 */ + /* D8 : WWAN_CONFIG_3 */ PAD_NC(GPP_D8, NONE), - /* TOUCHSCREEN_RST_L */ + /* D9 : GPP_D9 ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : GPP_D10 ==> NC */ + PAD_NC(GPP_D10, NONE), + /* D11 : GPP_D11 ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D12 : GPP_D12 */ + PAD_NC(GPP_D12, NONE), + /* D13 : ISH_UART_RX */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART_TX */ + PAD_NC(GPP_D14, NONE), + /* D15 : TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_D15, 0, DEEP), - /* - * TOUCHSCREEN_INT_L - * TODO Configure it back to invert mode, when - * ITSS IPCx configuration is fixed in FSP. - */ + /* D16 : USI_INT */ PAD_CFG_GPI_APIC(GPP_D16, NONE, DEEP, LEVEL, NONE), + /* D17 : PCH_HP_SDW_CLK */ + PAD_NC(GPP_D17, NONE), + /* D18 : PCH_HP_SDW_DAT */ + PAD_NC(GPP_D18, NONE), + /* D19 : DMIC_CLK_0_SNDW4_CLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* D20 : DMIC_DATA_0_SNDW4_DATA */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* - * TRACKPAD_INT_ODL + * D21 : TRACKPAD_INT_ODL * TODO Combine into single gpio with invert mode, when ITSS * IPCx configuration is fixed in FSP. */ PAD_CFG_GPI_APIC(GPP_D21, NONE, PLTRST, LEVEL, NONE), - /* SATAGP1 */ + /* D22 : GPP_D22 ==> NC */ + PAD_NC(GPP_D22, NONE), + /* D23 : SPP_MCLK */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E0 : GPP_E0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E1 : SATAGP1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), - /* M2_SSD_PE_WAKE_ODL */ + /* E2 : GPP_E2 ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E3 : GPP_E3 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : M2_SSD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_E4, NONE, DEEP), - /* SATA_DEVSLP1 */ + /* E5 : SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), - /* USB_C_OC_OD USB_OC2*/ + /* E6 : M2_SSD_RST_L */ + PAD_NC(GPP_E6, NONE), + /* E7 : GPP_E7 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E8 : GPP_E8 ==> NC */ + PAD_NC(GPP_E8, NONE), + /* E9 : GPP_E9 ==> NC */ + PAD_NC(GPP_E9, NONE), + /* E10 : GPP_E10 ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : USB_C_OC_OD USB_OC2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), - /* USB_A_OC_OD USB_OC3*/ + /* E12 : USB_A_OC_OD USB_OC3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - /* USB_C0_DP_HPD */ + /* E13 : USB_C0_DP_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), - /* DDI2_HPD_ODL */ + /* E14 : DDI2_HPD_ODL */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* DDPD_HPD2 => NC */ - PAD_NC(GPP_E15, DN_20K), - /* DDPE_HPD2 => NC */ - PAD_NC(GPP_E16, DN_20K), - /* EDP_HPD */ + /* E15 : DDPD_HPD2 => NC */ + PAD_NC(GPP_E15, NONE), + /* E16 : DDPE_HPD2 => NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), - /* DDPB_CTRLCLK => NC */ - PAD_NC(GPP_E18, DN_20K), - /* DDPC_CTRLCLK => NC */ - PAD_NC(GPP_E20, DN_20K), - /* DDPD_CTRLCLK => NC */ - PAD_NC(GPP_E22, DN_20K), - /* GPIO_WWAN_WLAN_COEX3 */ + /* E18 : DDPB_CTRLCLK => NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_CFG_GPI(GPP_E19, NONE, DEEP), + /* E20 : DDPC_CTRLCLK => NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_CFG_GPI(GPP_E21, NONE, DEEP), + /* E22 : DDPD_CTRLCLK => NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : GPP_E23_STRAP */ + PAD_NC(GPP_E23, NONE), + + /* F0 : GPIO_WWAN_WLAN_COEX3 */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), - /* WWAN_RESET_1V8_ODL */ + /* F1 : WWAN_RESET_1V8_ODL */ PAD_CFG_GPO(GPP_F1, 1, DEEP), - /* UART_WWANTX_WLANRX_COEX1 */ + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F3 : GPP_F3 ==> NC */ + PAD_NC(GPP_F3, NONE), + /* F4 : CNV_BRI_DT */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), + /* F6 : CNV_RGI_DT */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + /* F8 : UART_WWANTX_WLANRX_COEX1 */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), - /* UART_WWANRX_WLANTX_COEX2 */ + /* F9 : UART_WWANRX_WLANTX_COEX2 */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), - /* PCH_MEM_STRAP0 */ - PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* PCH_MEM_STRAP1 */ - PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* PCH_MEM_STRAP2 */ + /* F10 : GPP_F10 ==> NC */ + PAD_NC(GPP_F10, NONE), + /* F11 : PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_F11, NONE, PLTRST), - /* PCH_MEM_STRAP3 */ + /* F12 : GPP_F12 ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GPP_F13 ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GPP_F14 ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GPP_F15 ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GPP_F16 ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : GPP_F17 ==> NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : GPP_F18 ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : GPP_F19 ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_F22, NONE, PLTRST), - /* SD_CMD */ + /* F23 : GPP_F23 ==> NC */ + PAD_NC(GPP_F23, NONE), + + /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), - /* SD_DATA0 */ + /* G1 : SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), - /* SD_DATA1 */ + /* G2 : SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), - /* SD_DATA2 */ + /* G3 : SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), - /* SD_DATA3 */ + /* G4 : SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), - /* SD_CD# */ + /* G5 : SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), - /* SD_CLK */ + /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), - /* SD_WP => NC */ + /* G7 : SD_WP => NC */ PAD_NC(GPP_G7, DN_20K),
- /* PCH_I2C_PEN_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* PCH_I2C_PEN_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* PCH_I2C_SAR0_MST_SDA */ + /* + * H0 : AUDIO IRQ + * TODO Configure it back to invert mode, when + * ITSS IPCx configuration is fixed in FSP. + */ + PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, NONE), + /* H1 : CNV_RF_RESET_L */ + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), + /* H2 : CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), + /* H3 : SPEAKER SD MODE ENABLE */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H4 : PCH_I2C_PEN_SDA */ + PAD_NC(GPP_H4, NONE), + /* H5 : PCH_I2C_PEN_SCL */ + PAD_NC(GPP_H5, NONE), + /* H6 : PCH_I2C_SAR0_MST_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* PCH_I2C_SAR0_MST_SCL */ + /* H7 : PCH_I2C_SAR0_MST_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* PCH_I2C_M2_AUDIO_SAR1_SDA */ + /* H8 : PCH_I2C_M2_AUDIO_SAR1_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), - /* PCH_I2C_M2_AUDIO_SAR1_SCL */ + /* H9 : PCH_I2C_M2_AUDIO_SAR1_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), - /* PCH_I2C_TRACKPAD_SDA */ + /* H10 : PCH_I2C_TRACKPAD_SDA */ PAD_NC(GPP_H10, NONE), - /* PCH_I2C_TRACKPAD_SCL */ + /* H11 : PCH_I2C_TRACKPAD_SCL */ PAD_NC(GPP_H11, NONE), - /* SD card detect VGPIO */ - PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP), + /* H12 : GPP_H12 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : GPP_H13 ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H14 : GPP_H14 ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : GPP_H15 ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : GPP_H16 ==> NC */ + PAD_NC(GPP_H16, NONE), + /* H17 : TP1 */ + PAD_NC(GPP_H17, NONE), + /* H18 : CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : GPP_H19 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : TP41 */ + PAD_NC(GPP_H20, NONE), + /* H21 : XTAL_FREQ_SEL */ + PAD_NC(GPP_H21, NONE), + /* H22 : GPP_H22 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : GPP_H23_STRAP */ + PAD_NC(GPP_H23, NONE),
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + + /* SD card detect VGPIO */ + PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP), };
const struct pad_config *__weak variant_gpio_table(size_t *num) @@ -205,24 +410,35 @@
/* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { - /* H1_SLAVE_SPI_CS_L */ + /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_CLK */ + /* B16 : H1_SLAVE_SPI_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MISO_R */ + /* B17 : H1_SLAVE_SPI_MISO_R */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MOSI_R */ + /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* - * H1_PCH_INT_ODL + * C21 : H1_PCH_INT_ODL * TODO Configure it back to invert mode, when * ITSS IPCx configuration is fixed in FSP. */ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE), - /* WLAN_PE_RST# */ + /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), + };
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
-
Furquan Shaikh (Code Review) -
Paul Menzel (Code Review)
-
Shelley Chen (Code Review)