Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78648?usp=email )
Change subject: soc/intel/meteorlake: Consolidate settings for enabling tracehub ......................................................................
soc/intel/meteorlake: Consolidate settings for enabling tracehub
To get tracehub working, it requires few settings such as SOC_INTEL_METEORLAKE_DEBUG_CONSENT=2 and enable tracehub device in dev tree. This commit binds all tracehub related settings to Kconfig, so that users only need to enable SOC_INTEL_COMMON_BLOCK_TRACEHUB
TEST=boot on screebo and test tracehub device exists and working
Change-Id: Ie830fe2fd38e3456497bea37fe42ca60d26ca305 Signed-off-by: Kane Chen kane.chen@intel.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/78648 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subratabanik@google.com --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/chip.c 2 files changed, 16 insertions(+), 0 deletions(-)
Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 05d7f70..a2f2706 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -353,6 +353,7 @@ # USB DBC is more common for developers so make this default to 6 if # SOC_INTEL_DEBUG_CONSENT=y default 6 if SOC_INTEL_DEBUG_CONSENT + default 2 if SOC_INTEL_COMMON_BLOCK_TRACEHUB default 0 help This is to control debug interface on SOC. diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index a1b1968..be957cc 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -151,6 +151,18 @@ gpio_pm_configure(value, TOTAL_GPIO_COMM); }
+/* Enable tracehub in device tree */ +static void soc_enable_tracehub(void) +{ + struct device *dev; + + dev = pcidev_path_on_root(PCI_DEVFN_NPK); + if (dev) { + dev->enabled = 1; + printk(BIOS_DEBUG, "Tracehub is enabled.\n"); + } +} + void soc_init_pre_device(void *chip_info) { config_t *config = config_of_soc(); @@ -159,6 +171,9 @@ config->tbt_authentication = ioe_p2sb_sbi_read(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION;
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_TRACEHUB)) + soc_enable_tracehub(); + /* Perform silicon specific init. */ fsp_silicon_init();