[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Keith Hui (Code Review)]

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin.

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 6:

(2 comments)

Patchset:

PS6: 
Bill, since I also removed the PP/OD setting around GPIO bank 7 which overlaps with the 3 reset output pins, please watch for regressions around rebooting.

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/56656349_9d902c75?usp... :
PS2, Line 77: {7, 34, 20, -1}
> The `overridetree.cb` still specifies `drq 0xe4 = 0xfc` for `device pnp 2e. […]

Fix in. Thanks for the catch.

Goes to show that I need more sleep. -.-