Change in coreboot[master]: mainboard/prodrive: Add read FSP options form EEPROM

[Christian Walter (Code Review)]

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40408 )

Change subject: mainboard/prodrive: Add read FSP options form EEPROM
......................................................................

mainboard/prodrive: Add read FSP options form EEPROM

Change-Id: I27b11f60b1b335d50a31b2546442acf019fa7718
Signed-off-by: Christian Walter 
---
M src/mainboard/prodrive/hermes/mainboard.c
M src/mainboard/prodrive/hermes/romstage.c
M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
3 files changed, 101 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/40408/1

diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c
index d859e78..b2b737f 100644
--- a/src/mainboard/prodrive/hermes/mainboard.c
+++ b/src/mainboard/prodrive/hermes/mainboard.c
@@ -11,6 +11,8 @@
 #include <device/pci_def.h>
 #include <soc/pci_devs.h>
 #define HOSTC_I2C_EN (1 << 2)
+#define FSPS_SETTINGS_OFFSET 	0x0600
+#define FSPS_SETTINGS_SIZE		0x0c00

#include "gpio.h"

@@ -83,6 +85,7 @@

/* Enable I2C_EN bit in HOSTC register */
    smb_ctrl_reg = pci_read_config32(dev, HOSTC);
+	printk(BIOS_DEBUG, "SMB_CTROL_REG: %x\n", smb_ctrl_reg);
    pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN);

/* We can always read two bytes at a time */
@@ -111,15 +114,18 @@
    	hexdump(test, sizeof(test));
    }

-	mb_configure_dp1_pwr(0);
-	mb_configure_dp2_pwr(0);
-	mb_configure_dp3_pwr(0);
+	u16 hdaReg = pci_read_config16(PCH_DEV_HDA, 0);
+	printk(BIOS_DEBUG, "hdaReg: %x\n", hdaReg);
+
+	mb_configure_dp1_pwr(1);
+	mb_configure_dp2_pwr(1);
+	mb_configure_dp3_pwr(1);
    if (0) {
    	mb_pcie_reset_pch_slots(1);
    	mb_pcie_reset_cpu_slots(0);
    	mb_pcie_reset_cnvi_slot(0);
    }
-	mb_hda_amp_enable(0);
+	mb_hda_amp_enable(1);
    mb_usb31_rp1_pwr_enable(1);
    mb_usb31_rp2_pwr_enable(1);
    mb_usb31_fp_pwr_enable(1);
diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c
index 3372f3c..3b2d08d 100644
--- a/src/mainboard/prodrive/hermes/romstage.c
+++ b/src/mainboard/prodrive/hermes/romstage.c
@@ -6,18 +6,101 @@
 #include <variant/variants.h>
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
+#include <console/console.h>
+#include <device/smbus_host.h>
+
+#include <lib.h>
+
+#define REG_PCI_WRITE8(reg_, value_) \
+        REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0)
+#define REG_PCI_WRITE16(reg_, value_) \
+        REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0)
+#define REG_PCI_WRITE32(reg_, value_) \
+        REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0)
+
+#define HOSTC 0x40
+#define SMBUS_IO_BASE	0xefa0
+#define HOSTC_I2C_EN (1 << 2)
+
+#define FSPM_SETTINGS_OFFSET	0x0000
+#define FSPM_SETTINGS_SIZE		0x0600
+#define FSPM_SETTINGS_AMOUNT	3
+
+// FIX: ?
+static uint16_t fspm_settings[FSPM_SETTINGS_AMOUNT][2] = {
+	{0x0209, 1},
+	{0x020B, 1},
+	{0x00C4, 1}
+};
+
+// Read data from offset and write it to offset in UPD
+static bool read_write_config(u8 addr, FSPM_UPD *memupd)
+{
+	pci_devfn_t dev = PCI_DEV(0, PCH_DEV_SLOT_LPC, 4);
+
+	u32 smb_ctrl_reg;
+	int ret;
+
+	smb_ctrl_reg = pci_read_config32(dev, HOSTC);
+	printk(BIOS_DEBUG, "SMB CTRL REG: %x\n", smb_ctrl_reg);
+	pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN);
+	printk(BIOS_DEBUG, "SMB CTRL REG: %x\n", pci_read_config32(dev, HOSTC));
+
+	/* Loop through options, read it from flash and write it to
+	* UPD Struct
+	*/
+	for (u8 j = 0; j < FSPM_SETTINGS_AMOUNT; j++)
+	{
+		/* code */
+		printk(BIOS_DEBUG, "Offset: %04x - Size: %x\n", fspm_settings[j][0], fspm_settings[j][1]);
+	}
+
+	u8 blob[16];
+
+	/* We can always read two bytes at a time */
+	u8 i = 0;
+	for (i = 0; i < FSPM_SETTINGS_AMOUNT; i ++) {
+		u16 i_reverse = ((fspm_settings[i][0] & 0x00FF) << 8) | ((fspm_settings[i][0] & 0xFF00) >> 8);
+		ret = do_smbus_process_call(SMBUS_IO_BASE, addr, 0, i_reverse,
+				(uint16_t *)&blob[i]);
+		if (ret < 0)
+			return false;
+	}
+
+	hexdump(blob, sizeof(blob));
+
+	/* Restore I2C_EN bit */
+	pci_write_config32(dev, HOSTC, smb_ctrl_reg);
+
+	return true;
+}
+
+/*
+static bool read_config_with_offset(uintptr_t base, u8 addr, u16 offset, u8 *blob, u8 size)
+{
+	int ret;
+	u8 i;
+
+	// we need to change endianess here
+	for (i = 0; i < size; i++) {
+		u16 offset_flash = offset + i;
+		offset_flash = ((offset_flash & 0x00FF) << 8) | ((offset_flash & 0xFF00) >> 8);
+		ret = do_smbus_process_call(SMBUS_IO_BASE, addr, 0, offset_flash, (uint16_t *)&blob[i]);
+		if (ret < 0)
+			return false;
+	}
+
+	return true;
+}
+*/

void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	read_write_config(0x57, memupd);
+
    memupd->FspmConfig.UserBd = 7;
    memupd->FspmTestConfig.SmbusSpdWriteDisable = 0;
    memupd->FspmConfig.IedSize=0x400000;
    cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config());

-	/*
-	 * FIXME: Workaroung for SATA1 (M.2 SATA/PCIe) switchover breaking the SATA
-	 * SATA controller host reset, resulting in all SATA ports unusable.
-	 */
-	pci_write_config32(PCH_DEV_SATA, 0x90, (1 << 17));
-
 }
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
index db00e78..2659059 100644
--- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
@@ -101,8 +101,6 @@
    # Thermal
    register "tcc_offset" = "6"     # TCC of 94C

-	register "PchHdaDspEnable" = "1"
-
    # Enable "Intel Speed Shift Technology"
    register "speed_shift_enable" = "1"

@@ -119,7 +117,7 @@
    	.gspi[0] = {
    		.speed_mhz = 1,
    		.early_init = 1,
-		}
+		},
    }"

register "SerialIoDevMode" = "{
@@ -175,5 +173,6 @@
    		end
    	end # GSPI #0
    	device pci 1e.3 off end # GSPI #1
+
    end
 end