Change in coreboot[master]: soc/amd/stoneyridge: Create MMIO ACPI access functions

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29350

Change subject: soc/amd/stoneyridge: Create MMIO ACPI access functions
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soc/amd/stoneyridge: Create MMIO ACPI access functions

Now that the relationship between IO access and MMIO access has been
established, create read/write functions to access ACPI standard registers
through MMIO.

BUG=b:118049037
TEST=Build grunt

Change-Id: I8dab279019fe9ca55522ab3e65f51b9f459529ee
Signed-off-by: Richard Spiegel 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/sb_util.c
2 files changed, 36 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29350/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 681f149..6b96c81 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -444,6 +444,12 @@
 void pm_write8(u8 reg, u8 value);
 void pm_write16(u8 reg, u16 value);
 void pm_write32(u8 reg, u32 value);
+u8 acpi_mmio_read8(u8 reg);
+u16 acpi_mmio_read16(u8 reg);
+u32 acpi_mmio_read32(u8 reg);
+void acpi_mmio_write8(u8 reg, u8 value);
+void acpi_mmio_write16(u8 reg, u16 value);
+void acpi_mmio_write32(u8 reg, u32 value);
 u32 misc_read32(u8 reg);
 void misc_write32(u8 reg, u32 value);
 uint8_t smi_read8(uint8_t offset);
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index 9daf0bb..f6bfcc9 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -56,6 +56,36 @@
    return read32((void *)(PM_MMIO_BASE + reg));
 }

+u8 acpi_mmio_read8(u8 reg)
+{
+	return read8((u8 *)(ACPI_REG_MMIO_BASE + reg));
+}
+
+u16 acpi_mmio_read16(u8 reg)
+{
+	return read16((u16 *)(ACPI_REG_MMIO_BASE + reg));
+}
+
+u32 acpi_mmio_read32(u8 reg)
+{
+	return read32((u32 *)(ACPI_REG_MMIO_BASE + reg));
+}
+
+void acpi_mmio_write8(u8 reg, u8 value)
+{
+	write8((u8 *)(ACPI_REG_MMIO_BASE + reg), value);
+}
+
+void acpi_mmio_write16(u8 reg, u16 value)
+{
+	write16((u16 *)(ACPI_REG_MMIO_BASE + reg), value);
+}
+
+void acpi_mmio_write32(u8 reg, u32 value)
+{
+	write32((u32 *)(ACPI_REG_MMIO_BASE + reg), value);
+}
+
 void smi_write32(uint8_t offset, uint32_t value)
 {
    write32((void *)(APU_SMI_BASE + offset), value);