Patch set updated for coreboot: chromeos: vboot prefix removal on sw write protect state function
Paul Kocialkowski (contact@paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11496
-gerrit
commit af123cd6799f109afcb8758be348e84cb51bc907 Author: Paul Kocialkowski contact@paulk.fr Date: Thu Sep 3 11:27:27 2015 +0200
chromeos: vboot prefix removal on sw write protect state function
This removes the vboot prefix to the vboot_get_sw_write_protect function, since it is called from soc code and doesn't really have to be tied to vboot.
Its name is also refactored to be consistent with the previous definition of get_write_protect_state.
Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6 Signed-off-by: Paul Kocialkowski contact@paulk.fr --- src/soc/intel/baytrail/romstage/romstage.c | 2 +- src/soc/intel/broadwell/romstage/romstage.c | 2 +- src/soc/intel/skylake/romstage/romstage.c | 2 +- src/vendorcode/google/chromeos/chromeos.c | 2 +- src/vendorcode/google/chromeos/chromeos.h | 2 +- src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 1b93eb6..dbd69be 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -363,7 +363,7 @@ void ramstage_cache_invalid(void) }
#if CONFIG_CHROMEOS -int vboot_get_sw_write_protect(void) +int get_sw_write_protect_state(void) { u8 status; /* Return unprotected status if status read fails. */ diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 27fb0f2..bc8cb3f 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -148,7 +148,7 @@ void ramstage_cache_invalid(void) }
#if CONFIG_CHROMEOS -int vboot_get_sw_write_protect(void) +int get_sw_write_protect_state(void) { u8 status; /* Return unprotected status if status read fails. */ diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 91a496e..e9b7243 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -67,7 +67,7 @@ void soc_romstage_init(struct romstage_params *params) }
#if IS_ENABLED(CONFIG_CHROMEOS) -int vboot_get_sw_write_protect(void) +int get_sw_write_protect_state(void) { u8 status;
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index 0737267..c2190b7 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -65,7 +65,7 @@ void __attribute__((weak)) save_chromeos_gpios(void) // Can be implemented by a mainboard }
-int __attribute__((weak)) vboot_get_sw_write_protect(void) +int __attribute__((weak)) get_sw_write_protect_state(void) { // Can be implemented by a platform / mainboard return 0; diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index c7048dd..d3fb8e9 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -68,7 +68,7 @@ static inline int vboot_get_handoff_info(void **addr, uint32_t *size) } #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
-int vboot_get_sw_write_protect(void); +int get_sw_write_protect_state(void);
#include "gnvs.h" struct device; diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c index c8ba114..8e12fdc 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c @@ -61,7 +61,7 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff,
if (get_write_protect_state()) vb_sd->flags |= VBSD_BOOT_FIRMWARE_WP_ENABLED; - if (vboot_get_sw_write_protect()) + if (get_sw_write_protect_state()) vb_sd->flags |= VBSD_BOOT_FIRMWARE_SW_WP_ENABLED;
if (vb2_sd->recovery_reason) {
-
Paul Kocialkowski