Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28289
Change subject: util/msrtool: Fix typo ......................................................................
util/msrtool: Fix typo
Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/msrtool/intel_atom.c M util/msrtool/intel_core2_later.c M util/msrtool/intel_nehalem.c 3 files changed, 22 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/28289/1
diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index f2df5ae..489e0a0 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -278,7 +278,7 @@ }}, { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, { /* This bit enables a system executive to use - * VMX in conjuction with SMX to support Intel + * VMX in conjunction with SMX to support Intel * Trusted Execution Technology. */ { MSR1(0), "VMX inside of SMX operation disabled" }, @@ -797,9 +797,9 @@ /* if CPUID.0AH EAX[7:0] > 2 */ { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { @@ -820,9 +820,9 @@ /* if CPUID.0AH: EAX[7:0] > 2 */ { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { @@ -843,9 +843,9 @@ /* if CPUID.0AH: EAX[7:0] > 2 */ { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index 4bb0097..95e8e91 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -232,7 +232,7 @@ }}, { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, { /* This bit enables a system executive to use - * VMX in conjuction with SMX to support Intel + * VMX in conjunction with SMX to support Intel * Trusted Execution Technology. */ { MSR1(0), "VMX inside of SMX operation disabled" }, @@ -821,9 +821,9 @@ /* if CPUID.0AH EAX[7:0] > 2 */ { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { @@ -844,9 +844,9 @@ /* if CPUID.0AH: EAX[7:0] > 2 */ { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { @@ -867,9 +867,9 @@ /* if CPUID.0AH: EAX[7:0] > 2 */ { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index 11acdd8..726ad0a 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -307,7 +307,7 @@ }}, { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, { /* This bit enables a system executive to use - * VMX in conjuction with SMX to support Intel + * VMX in conjunction with SMX to support Intel * Trusted Execution Technology. */ { MSR1(0), "VMX inside of SMX operation disabled" }, @@ -1109,7 +1109,7 @@ /* Whole package bit */ { 1, 1, "C1E Enable", "R/W", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "CPU switch to the Minimum Enhaced Intel \ + { MSR1(1), "CPU switch to the Minimum Enhanced Intel \ SpeedStep Technology operating point when all \ execution cores enter MWAIT (C1)" }, { BITVAL_EOT } @@ -1373,9 +1373,9 @@ /* if CPUID.0AH EAX[7:0] > 2 */ { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { @@ -1396,9 +1396,9 @@ /* if CPUID.0AH: EAX[7:0] > 2 */ { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { @@ -1419,9 +1419,9 @@ /* if CPUID.0AH: EAX[7:0] > 2 */ { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { { MSR1(0), "Counter only increments the associated event \ - conditions occuring in the logical processor which programmed the MSR" }, + conditions occurring in the logical processor which programmed the MSR" }, { MSR1(1), "Counting the associated event conditions \ - occuring across all logical processors sharing a processor core" }, + occurring across all logical processors sharing a processor core" }, { BITVAL_EOT } }}, { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
-
Elyes HAOUAS (Code Review)