Change in coreboot[master]: soc/intel/alderlake: Update iDisp Link UPD settings

[Francois Toguo Fotso (Code Review)]

Attention is currently required from: Sathyanarayana Nujella, Varshit B Pandya, Subrata Banik, Furquan Shaikh, Maulik V Vaghela, Paul Menzel, Angel Pons, Ronak Kanabar, Jairaj Arava, Patrick Rudolph.
Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51353 )

Change subject: soc/intel/alderlake: Update iDisp Link UPD settings
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Patch Set 7:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/51353/comment/cbbd1e89_8fc2d1e0 
PS6, Line 9: These UPD values are automatically set by the FSP.
> I can't claim to understand this completely, but based on the limited information I have seen this s […]

Not quite sure I understand the rational in "..common code should set UPDs as follows.." .There are no UPD settings in common code that I know of, rather they are done in fsp_param.c, which are always specific to each SOC, not common.

Since there is no "common" UPD setting, I don't see the benefit of introducing a new config here.

Additionally, the suggestion to set the default PchHdaIDispLinkTmode -> 4T also won't work. For TGL it was the default value, and may have worked. But for ADL we had to switch to 8T for it to work properly. Please see the first set of this CL.
For me, it still makes sense to use the devicetree in mainboard to set the proper register values which are passed to UPDs in fsp_param.c (as originally done in patchset 1 & 2), and drop the subsequent changes (in patchset 3 onward)