[XS] Change in coreboot[main]: mb/google/brya/var/anahera: Enable RTD3 for SSD to resolve S0ix issue

[Pranava Y N (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik.

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87057?usp=email )

Change subject: mb/google/brya/var/anahera: Enable RTD3 for SSD to resolve S0ix issue
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mb/google/brya/var/anahera: Enable RTD3 for SSD to resolve S0ix issue

Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.

Enable and reset GPIOs are configured as per pin mapping in gpio.c.

BUG=b:391612392
TEST=Run suspend_stress_test on anahera device and verify that the
device suspends to S0ix.

Change-Id: I43a1277efabf8b1ca265e9aca65878da60275b38
Signed-off-by: Pranava Y N 
---
M src/mainboard/google/brya/variants/anahera/overridetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/87057/1

diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index 2670e11..1256608 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -227,6 +227,15 @@
    			device generic 0 on end
    		end
    	end	#PCIE8 SD card
+		device ref pcie_rp9 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "1"
+				device generic 0 on end
+			end
+		end	#PCIE9-12 SSD
    	device ref i2c0 on
    		chip drivers/i2c/generic
    			register "hid" = ""10EC5682""