Hello Ivy Jian,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/42740
to review the following change.
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
mb/google/sarien: Enable bayhub 720 on Sarien
Add PCIe-eMMC bridge bayhub 720 on Sarien.
BUG=b:157971972 BRANCH=sarien TEST=local build and boot from storage successfully
Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329 Signed-off-by: Frank Wu frank_wu@compal.corp-partner.google.com --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/sarien/Makefile.inc M src/mainboard/google/sarien/variants/sarien/devicetree.cb A src/mainboard/google/sarien/variants/sarien/mainboard.c 4 files changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42740/1
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index df5e5b8..53b9243 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BH720 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH if BOARD_GOOGLE_ARCADA diff --git a/src/mainboard/google/sarien/variants/sarien/Makefile.inc b/src/mainboard/google/sarien/variants/sarien/Makefile.inc index eff19f5..238c6e9 100644 --- a/src/mainboard/google/sarien/variants/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/variants/sarien/Makefile.inc @@ -2,5 +2,6 @@
bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += mainboard.c romstage-y += gpio.c verstage-y += gpio.c diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 09b4240..24bccc0 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -395,12 +395,20 @@ device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on end # PCI Express Port 8 device pci 1d.0 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 diff --git a/src/mainboard/google/sarien/variants/sarien/mainboard.c b/src/mainboard/google/sarien/variants/sarien/mainboard.c new file mode 100644 index 0000000..f4df8b4 --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/mainboard.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/mmio.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <drivers/generic/bayhub/bh720.h> +#include <string.h> + +void board_bh720(struct device *dev) +{ + u32 sdbar; + u32 bh720_pcr_data; + + printk(BIOS_DEBUG, "mainboard: board_bh720 init\n"); + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_CSR); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_CSR); + + /* Disable Memory Access */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42740/1/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/sarien/mainboard.c:
https://review.coreboot.org/c/coreboot/+/42740/1/src/mainboard/google/sarien... PS1, Line 28: printk(BIOS_DEBUG, "mainboard: board_bh720 init\n"); Prefer using '"%s...", __func__' to using 'board_bh720', this function's name, in a string
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Mathew King, Duncan Laurie, Ivy Jian, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42740
to look at the new patch set (#2).
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
mb/google/sarien: Enable bayhub 720 on Sarien
Add PCIe-eMMC bridge bayhub 720 on Sarien.
BUG=b:157971972 BRANCH=sarien TEST=local build and boot from storage successfully
Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329 Signed-off-by: Frank Wu frank_wu@compal.corp-partner.google.com --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/sarien/Makefile.inc M src/mainboard/google/sarien/variants/sarien/devicetree.cb A src/mainboard/google/sarien/variants/sarien/mainboard.c 4 files changed, 65 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42740/2
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 2:
Should this be enabled on Arcada as well?
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 2:
Patch Set 2:
Should this be enabled on Arcada as well?
They uploaded their CL for Arcada below. https://review.coreboot.org/c/coreboot/+/42769
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Should this be enabled on Arcada as well?
They uploaded their CL for Arcada below. https://review.coreboot.org/c/coreboot/+/42769
Because this is identical between the two can you move it to a common location?
Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Mathew King, Duncan Laurie, Ivy Jian, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42740
to look at the new patch set (#3).
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
mb/google/sarien: Enable bayhub 720 on Sarien
Add PCIe-eMMC bridge bayhub 720 on Sarien.
BUG=b:157971972 BRANCH=sarien TEST=local build and boot from storage successfully
Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329 Signed-off-by: Frank Wu frank_wu@compal.corp-partner.google.com --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/Makefile.inc A src/mainboard/google/sarien/mainboard.c M src/mainboard/google/sarien/variants/sarien/devicetree.cb 4 files changed, 65 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42740/3
Frank Wu has removed Paul Menzel from this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Removed reviewer Paul Menzel.
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 3:
Hi Mat,
I move the codes from variant to common. Would you help review? Thank you.
Frank Wu has removed Patrick Georgi from this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Removed reviewer Patrick Georgi.
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 3:
Patch Set 2:
Patch Set 2:
Patch Set 2:
Should this be enabled on Arcada as well?
They uploaded their CL for Arcada below. https://review.coreboot.org/c/coreboot/+/42769
Because this is identical between the two can you move it to a common location?
Update patchset3. Would you help to review it?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42740/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42740/3//COMMIT_MSG@9 PS3, Line 9: Add PCIe-eMMC bridge bayhub 720 on Sarien. Why is the mainboard code needed, and can’t be in the common driver?
Please mention the datasheet and version you used.
https://review.coreboot.org/c/coreboot/+/42740/3/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42740/3/src/mainboard/google/sarien... PS3, Line 401: end Please consistently use tabs for indentation.
Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Mathew King, Duncan Laurie, Ivy Jian, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42740
to look at the new patch set (#4).
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
mb/google/sarien: Enable bayhub 720 on Sarien
Add PCIe-eMMC bridge bayhub 720 on Sarien.
BUG=b:157971972 BRANCH=sarien TEST=local build and boot from storage successfully
Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329 Signed-off-by: Frank Wu frank_wu@compal.corp-partner.google.com --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/Makefile.inc A src/mainboard/google/sarien/mainboard.c M src/mainboard/google/sarien/variants/sarien/devicetree.cb 4 files changed, 65 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42740/4
Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4: Code-Review+2
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4: Code-Review+2
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42740/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42740/3//COMMIT_MSG@9 PS3, Line 9: Add PCIe-eMMC bridge bayhub 720 on Sarien.
Why is the mainboard code needed, and can’t be in the common driver? […]
We reference grunt.
https://review.coreboot.org/c/coreboot/+/42740/3/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42740/3/src/mainboard/google/sarien... PS3, Line 401: end
Please consistently use tabs for indentation.
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4: Code-Review+2
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4:
Hi Mat and Duncan,
Would you help merged the CL? Then we can verify this with CPFE FW. Thank you.
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4: -Code-Review
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4: Code-Review+2
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42740/4/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42740/4/src/mainboard/google/sarien... PS4, Line 388: device pci 1a.0 off end # eMMC : device pci 1c.0 on end # PCI Express Port 1 (USB) : device pci 1c.1 off end # PCI Express Port 2 (USB) : device pci 1c.2 off end # PCI Express Port 3 (USB) : device pci 1c.3 off end # PCI Express Port 4 (USB) : device pci 1c.4 off end # PCI Express Port 5 (USB) : device pci 1c.5 off end # PCI Express Port 6 : device pci 1c.6 off end # PCI Express Port 7 : device pci 1c.7 on end # PCI Express Port 8 : device pci 1d.0 on : chip drivers/generic/bayhub : register "power_saving" = "1" : device pci 00.0 on end : end : smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" : end # PCI Express Port 9 : device pci 1d.1 on end # PCI Express Port 10 : device pci 1d.2 off end # PCI Express Port 11 : device pci 1d.3 off end # PCI Express Port 12 : device pci 1d.4 on : chip drivers/generic/bayhub : register "power_saving" = "1" : device pci 00.0 on end : end : smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" : end # PCI Express Port 13 (x4) : device pci 1e.0 off end # UART #0 : device pci 1e.1 off end # UART #1 : device pci 1e.2 off end # GSPI #0 : device pci 1e.3 off end # GSPI #1 : device pci 1f.0 on : chip ec/google/wilco : device pnp 0c09.0 on end : end This is also needed on Arcada as well as there is no shared devicetree.cb, correct?
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42740/4/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42740/4/src/mainboard/google/sarien... PS4, Line 388: device pci 1a.0 off end # eMMC : device pci 1c.0 on end # PCI Express Port 1 (USB) : device pci 1c.1 off end # PCI Express Port 2 (USB) : device pci 1c.2 off end # PCI Express Port 3 (USB) : device pci 1c.3 off end # PCI Express Port 4 (USB) : device pci 1c.4 off end # PCI Express Port 5 (USB) : device pci 1c.5 off end # PCI Express Port 6 : device pci 1c.6 off end # PCI Express Port 7 : device pci 1c.7 on end # PCI Express Port 8 : device pci 1d.0 on : chip drivers/generic/bayhub : register "power_saving" = "1" : device pci 00.0 on end : end : smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" : end # PCI Express Port 9 : device pci 1d.1 on end # PCI Express Port 10 : device pci 1d.2 off end # PCI Express Port 11 : device pci 1d.3 off end # PCI Express Port 12 : device pci 1d.4 on : chip drivers/generic/bayhub : register "power_saving" = "1" : device pci 00.0 on end : end : smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" : end # PCI Express Port 13 (x4) : device pci 1e.0 off end # UART #0 : device pci 1e.1 off end # UART #1 : device pci 1e.2 off end # GSPI #0 : device pci 1e.3 off end # GSPI #1 : device pci 1f.0 on : chip ec/google/wilco : device pnp 0c09.0 on end : end
This is also needed on Arcada as well as there is no shared devicetree. […]
Yes, there is no basedboard devicetree.cb for Sarien and Arcada. Therefore, those settings should be filled in each devicetree.cb .
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42740/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42740/3//COMMIT_MSG@9 PS3, Line 9: Add PCIe-eMMC bridge bayhub 720 on Sarien.
We reference grunt.
Sorry, I do not understand your reply.
Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42740/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42740/3//COMMIT_MSG@9 PS3, Line 9: Add PCIe-eMMC bridge bayhub 720 on Sarien.
Sorry, I do not understand your reply.
Here is the reference for bh720. https://github.com/coreboot/coreboot/blob/master/src/mainboard/google/kahlee...
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
mb/google/sarien: Enable bayhub 720 on Sarien
Add PCIe-eMMC bridge bayhub 720 on Sarien.
BUG=b:157971972 BRANCH=sarien TEST=local build and boot from storage successfully
Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329 Signed-off-by: Frank Wu frank_wu@compal.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42740 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Ivy Jian ivy_jian@compal.corp-partner.google.com Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Reviewed-by: Mathew King mathewk@chromium.org --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/Makefile.inc A src/mainboard/google/sarien/mainboard.c M src/mainboard/google/sarien/variants/sarien/devicetree.cb 4 files changed, 65 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Ivy Jian: Looks good to me, approved EricR Lai: Looks good to me, approved Mathew King: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index df5e5b8..53b9243 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BH720 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH if BOARD_GOOGLE_ARCADA diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index eea7f47..e7bfc53 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -2,6 +2,7 @@
bootblock-y += bootblock.c
+ramstage-y += mainboard.c ramstage-y += ramstage.c ramstage-y += sku.c
diff --git a/src/mainboard/google/sarien/mainboard.c b/src/mainboard/google/sarien/mainboard.c new file mode 100644 index 0000000..5399e6c --- /dev/null +++ b/src/mainboard/google/sarien/mainboard.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <drivers/generic/bayhub/bh720.h> +#include <string.h> + +void board_bh720(struct device *dev) +{ + u32 sdbar; + u32 bh720_pcr_data; + + printk(BIOS_DEBUG, "mainboard: %s init\n", __func__); + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_CSR); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_CSR); + + /* Disable Memory Access */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); +} diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 09b4240..1a8e624 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -395,12 +395,20 @@ device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on end # PCI Express Port 8 device pci 1d.0 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0
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