[S] Change in coreboot[main]: soc/intel/adl: Fill in SPD data on both channels of DDR5 memory

[Tim Crawford (Code Review)]

Attention is currently required from: Angel Pons, Dinesh Gehlot, Jeremy Soller, Kapil Porwal, Nick Vaccaro, Subrata Banik, Tarun Tuli.

Hello Dinesh Gehlot, Jeremy Soller, Kapil Porwal, Nick Vaccaro, Subrata Banik, Tarun Tuli, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/75284?usp=email

to look at the new patch set (#7).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/adl: Fill in SPD data on both channels of DDR5 memory
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soc/intel/adl: Fill in SPD data on both channels of DDR5 memory

CB:52731 introduced support for reading SPD from the EEPROM via SMBus.
Replace the now unneeded workaround for DDR5 with filling in the correct
channels for DDR5.

Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller 
Signed-off-by: Tim Crawford 
---
M src/soc/intel/alderlake/meminit.c
1 file changed, 15 insertions(+), 27 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/75284/7