Change in coreboot[master]: mb/google/brya/var/taeko: disabled autonomous GPIO power management

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59325 )

Change subject: mb/google/brya/var/taeko: disabled autonomous GPIO power management
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mb/google/brya/var/taeko: disabled autonomous GPIO power management

Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:205315500
TEST=emerge-brya coreboot and test that DUT can boot to OS.

Signed-off-by: Joey Peng 
Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59325
Tested-by: build bot (Jenkins) 
Reviewed-by: YH Lin 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
1 file changed, 10 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  YH Lin: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index d6d7c9b..a482363 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -41,6 +41,16 @@
    end
 end
 chip soc/intel/alderlake
+	# This disabled autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
    register "ext_fivr_settings" = "{
    	.configure_ext_fivr = 1,
    	.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,