Change in coreboot[master]: pci_def.h: Introduce PCI_EXP_DEVCAP2 & PCI_EXP_DEVCTL2 proper

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51327 )

Change subject: pci_def.h: Introduce PCI_EXP_DEVCAP2 & PCI_EXP_DEVCTL2 proper
......................................................................

pci_def.h: Introduce PCI_EXP_DEVCAP2 & PCI_EXP_DEVCTL2 proper

Replace the existing, odd looking, unordered definitions used for
LTR configuration with the usual names used by upstream libpci.

TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes.

Fixes: Code looked like UEFI copy-pasta. Header file was a mess.
Change-Id: Icf666692e22730e1bdf4bcdada433b3219af568a
Signed-off-by: Nico Huber 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51327
Reviewed-by: Angel Pons 
Reviewed-by: Aaron Durbin 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/device/pciexp_device.c
M src/include/device/pci_def.h
2 files changed, 8 insertions(+), 10 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 3153e0e..0b7c649 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -140,9 +140,9 @@
 {
    unsigned int val;

-	val = pci_read_config16(dev, cap + PCI_EXP_DEV_CAP2_OFFSET);
+	val = pci_read_config16(dev, cap + PCI_EXP_DEVCAP2);

-	if (val & LTR_MECHANISM_SUPPORT)
+	if (val & PCI_EXP_DEVCAP2_LTR)
    	return true;

return false;
@@ -164,10 +164,10 @@
    	return;
    }

-	cap += PCI_EXP_DEV_CTL_STS2_CAP_OFFSET;
+	cap += PCI_EXP_DEVCTL2;

/* Enable LTR for device */
-	pci_update_config32(dev, cap, ~LTR_MECHANISM_EN, LTR_MECHANISM_EN);
+	pci_update_config32(dev, cap, ~PCI_EXP_DEV2_LTR, PCI_EXP_DEV2_LTR);

/* Configure Max Snoop Latency */
    pciexp_config_max_latency(dev->bus->dev, dev);
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index e0d891e..b0558fa 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -386,12 +386,6 @@
 #define PCI_EXP_DEVCAP		4	/* Device capabilities */
 #define  PCI_EXP_DEVCAP_PAYLOAD	0x07	/* Max_Payload_Size */
 #define  PCI_EXP_DEVCAP_PHANTOM	0x18	/* Phantom functions */
-#define PCI_EXP_DEV_CAP2_OFFSET	0x24	/* Device Capabilities 2 offset */
-/* LTR mechanism supported.Bit 11 of Device Cap 2 Register */
-#define  LTR_MECHANISM_SUPPORT	(1 << 11)
-#define PCI_EXP_DEV_CTL_STS2_CAP_OFFSET	0x28	/* Device Control 2  offset */
-/* LTR mechanism enable. Bit 10 of Device Control 2 Register */
-#define  LTR_MECHANISM_EN	(1 << 10)
 #define  PCI_EXP_DEVCAP_EXT_TAG	0x20	/* Extended tags */
 #define  PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
 #define  PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
@@ -445,6 +439,10 @@
 #define  PCI_EXP_RTCTL_CRSSVE	0x10	/* CRS Software Visibility Enable */
 #define PCI_EXP_RTCAP		30	/* Root Capabilities */
 #define PCI_EXP_RTSTA		32	/* Root Status */
+#define PCI_EXP_DEVCAP2		36	/* Device capabilities 2 */
+#define  PCI_EXP_DEVCAP2_LTR	0x0800	/* LTR supported */
+#define PCI_EXP_DEVCTL2		40	/* Device Control 2 */
+#define  PCI_EXP_DEV2_LTR	0x0400	/* LTR enabled */

/* Extended Capabilities (PCI-X 2.0 and Express) */
 #define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)