[M] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_add_dram_resources

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81110?usp=email )

Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................

soc/intel/xeon_sp: Add soc_add_dram_resources

SoC specific DRAM resource, e.g. 4GB above memory map, are
different acorss SoC generations.

TEST=intel/archercity CRB

Change-Id: I8b0bb8e8c51ef20467958826b9fdd5a995e14901
Signed-off-by: Shuo Liu 
---
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore.c
2 files changed, 45 insertions(+), 24 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81110/1

diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h
index 729ab58..f4a028f 100644
--- a/src/soc/intel/xeon_sp/include/soc/chip_common.h
+++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h
@@ -54,6 +54,7 @@

void soc_create_ioat_domains(union xeon_domain_path path, struct bus *bus, const STACK_RES *sr);
 void soc_create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, const STACK_RES *sr);
+int soc_add_dram_resources(struct device *dev, int start_index);

struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device);
 struct device *dev_find_all_devices_on_socket(uint8_t socket, u16 vendor, u16 device, struct device *from);
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 952ca4d..4c94d61 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -8,6 +8,7 @@
 #include <device/pci_ids.h>
 #include <drivers/ocp/include/vpd.h>
 #include <soc/acpi.h>
+#include <soc/chip_common.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
@@ -197,10 +198,10 @@
  * +--------------------------+ 0
  */

+uint64_t mc_values[NUM_MAP_ENTRIES];
 static void mc_add_dram_resources(struct device *dev, int *res_count)
 {
    const struct resource *res;
-	uint64_t mc_values[NUM_MAP_ENTRIES];
    uint64_t top_of_ram;
    int index = *res_count;
    struct range_entry fsp_mem;
@@ -266,6 +267,47 @@
    			   mc_values[TOLM_REG]);
    LOG_RESOURCE("mmio_tolm", dev, res);

+	/* Add SoC specific resources */
+	index += soc_add_dram_resources(dev, index);
+
+	/* add MMIO CFG resource */
+	res = mmio_from_to(dev, index++, mc_values[MMCFG_BASE_REG],
+			   mc_values[MMCFG_LIMIT_REG] + 1);
+	LOG_RESOURCE("mmiocfg_res", dev, res);
+
+	/* add Local APIC resource */
+	res = mmio_range(dev, index++, LAPIC_DEFAULT_BASE, 0x00001000);
+	LOG_RESOURCE("apic_res", dev, res);
+
+	/*
+	 * Add legacy region as reserved - 0xa000 - 1MB
+	 * Reserve everything between A segment and 1MB:
+	 *
+	 * 0xa0000 - 0xbffff: legacy VGA
+	 * 0xc0000 - 0xfffff: RAM
+	 */
+	res = mmio_range(dev, index++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
+	LOG_RESOURCE("legacy_mmio", dev, res);
+
+	res = reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
+	LOG_RESOURCE("legacy_write_protect", dev, res);
+
+	*res_count = index;
+}
+
+/*
+ * Add SoC specific DRAM resources
+ *
+ * @param dev Pointer of the device to add resource on.
+ * @param start_index The start index for the SoC specific resources.
+ *
+ * @return Ahe added resource counts.
+ */
+int soc_add_dram_resources(struct device *dev, int start_index)
+{
+	const struct resource *res;
+	int index = start_index;
+
    if (CONFIG(SOC_INTEL_HAS_CXL)) {
    	/* 4GiB -> CXL Memory */
    	uint32_t gi_mem_size;
@@ -310,29 +352,7 @@
    	LOG_RESOURCE("high_ram", dev, res);
    }

-	/* add MMIO CFG resource */
-	res = mmio_from_to(dev, index++, mc_values[MMCFG_BASE_REG],
-			   mc_values[MMCFG_LIMIT_REG] + 1);
-	LOG_RESOURCE("mmiocfg_res", dev, res);
-
-	/* add Local APIC resource */
-	res = mmio_range(dev, index++, LAPIC_DEFAULT_BASE, 0x00001000);
-	LOG_RESOURCE("apic_res", dev, res);
-
-	/*
-	 * Add legacy region as reserved - 0xa000 - 1MB
-	 * Reserve everything between A segment and 1MB:
-	 *
-	 * 0xa0000 - 0xbffff: legacy VGA
-	 * 0xc0000 - 0xfffff: RAM
-	 */
-	res = mmio_range(dev, index++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
-	LOG_RESOURCE("legacy_mmio", dev, res);
-
-	res = reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
-	LOG_RESOURCE("legacy_write_protect", dev, res);
-
-	*res_count = index;
+	return index - start_index;
 }

static void mmapvtd_read_resources(struct device *dev)