Brandon Weeks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86260?usp=email )
Change subject: mb/cwwk/adl: Various device tree fixes ......................................................................
mb/cwwk/adl: Various device tree fixes
- Set pmc_gpe0_dw{0-3} to resolve a warning - Set CLKREQ# based on register value from vendor firmware - Enable ITE environment controller
Change-Id: I9365e76c593b7e4a334dcdc5ecd46da253e14716 Signed-off-by: Brandon Weeks bweeks@google.com --- M src/mainboard/cwwk/adl/devicetree.cb 1 file changed, 33 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/86260/1
diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb index 72a1a98..1284ddf 100644 --- a/src/mainboard/cwwk/adl/devicetree.cb +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -1,6 +1,8 @@ chip soc/intel/alderlake
- register "s0ix_enable" = "true" + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E"
register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" @@ -14,37 +16,40 @@ register "pch_pcie_rp[PCH_RP(1)]" = "{ .clk_src = 0, .clk_req = 0, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_CLK_REQ_DETECT, }"
register "pch_pcie_rp[PCH_RP(7)]" = "{ .clk_src = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .pcie_rp_aspm = ASPM_DISABLE, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_L0S, }"
register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 2, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .pcie_rp_aspm = ASPM_DISABLE, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_L0S, }"
register "pch_pcie_rp[PCH_RP(10)]" = "{ .clk_src = 3, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .pcie_rp_aspm = ASPM_DISABLE, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_L0S, }"
register "pch_pcie_rp[PCH_RP(11)]" = "{ .clk_src = 4, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, - .pcie_rp_aspm = ASPM_DISABLE, + .flags = PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_L0S, }"
register "pch_pcie_rp[PCH_RP(12)]" = "{ .clk_src = 4, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, - .pcie_rp_aspm = ASPM_DISABLE, + .flags = PCIE_RP_CLK_REQ_UNUSED, + .pcie_rp_aspm = ASPM_L0S, }"
# Enable EDP in PortA @@ -52,7 +57,6 @@
device domain 0 on device ref igpu on end - device ref dtt on end device ref crashlog off end device ref xhci on end device ref shared_sram on end @@ -63,18 +67,28 @@ device ref pcie_rp11 on end device ref pcie_rp12 on end # M.2 E key port device ref pch_espi on + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c0081" chip superio/ite/it8613e + register "FAN2.mode" = "FAN_SMART_SOFTWARE" # CPU_FAN + register "FAN3.mode" = "FAN_SMART_SOFTWARE" # SYS_FAN device pnp 2e.0 off end - device pnp 2e.1 on # COM 1 + device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 irq 0x70 = 0x4 irq 0xf0 = 0x1 end - device pnp 2e.4 off end # Environment Controller - device pnp 2e.5 off end # Keyboard - device pnp 2e.6 off end # Mouse - device pnp 2e.7 off end # GPIO - device pnp 2e.a off end # CIR + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + irq 0x70 = 0x00 + irq 0x71 = 0x80 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR end end device ref hda on end
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Brandon Weeks (Code Review)