Change in coreboot[master]: soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63167 )

Change subject: soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG
......................................................................

soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG

This patch binds all FSP-M and FSP-S UPDs required for serial
redirection with `FSP_ENABLE_SERIAL_DEBUG` config to allow coreboot to
choose when to enable FSP debug output redirection to serial port.
For example:
PcdSerialDebugLevel => For controlling FSP debug level between FSP-M/S
SerialDebugMrcLevel => For controllig MRC debug level.

With this change FSP debug output will only be enabled when the user
enables `FSP_ENABLE_SERIAL_DEBUG` from site-local config with coreboot
serial image.

BUG=b:225544587
TEST=Able to build and boot brya. Also, the FSP debug log is exactly
the same before and with this code change.

Signed-off-by: Subrata Banik 
Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63167
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Lean Sheng Tan 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 20 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Lean Sheng Tan: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 723ad92..157bf35 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -511,8 +511,10 @@
 static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
-	if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER))
-		s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)fsp_debug_event_handler);
+	if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) &&
+			 CONFIG(FSP_ENABLE_SERIAL_DEBUG))
+		s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
+				fsp_debug_event_handler);
    /* PCH UART selection for FSP Debug */
    s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
    ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index fe21b41..83ce074 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -324,9 +324,6 @@
 static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
-	/* Set MRC debug level */
-	m_cfg->SerialDebugMrcLevel = fsp_map_console_log_level();
-
    /* Set debug probe type */
    m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;

@@ -367,10 +364,22 @@
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
    FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;

-	if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER))
-		arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
-						fsp_debug_event_handler);
-
+	if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) {
+		if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) {
+			enum fsp_log_level log_level = fsp_map_console_log_level();
+			arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
+					fsp_debug_event_handler);
+			/* Set Serial debug message level */
+			m_cfg->PcdSerialDebugLevel = log_level;
+			/* Set MRC debug level */
+			m_cfg->SerialDebugMrcLevel = log_level;
+		} else {
+			/* Disable Serial debug message */
+			m_cfg->PcdSerialDebugLevel = 0;
+			/* Disable MRC debug message */
+			m_cfg->SerialDebugMrcLevel = 0;
+		}
+	}
    config = config_of_soc();

soc_memory_init_params(m_cfg, config);