[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Bill XIE (Code Review)]

Attention is currently required from: Keith Hui.

Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 1:

(1 comment)

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/7d2a72e3_588dd851?usp... :
PS1, Line 67: gpio5 |= 0x20;
Sadly, I installed a card onto PCIEX1_2 with pciepcs1 == 0 and force_asm1061 == 0, and inteltool said that GP_LVL == 0xe8ab7ffe (get_gpio(20) == 0), but pcie_rp4 remains wired to ASM1061, and superiotool said so:

LDN 0x09 (GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8)
idx 30 ... f4 f5 ...
val ff ... fc 88 ...
def 00 ... ff 00 ...

(Besides, overridetree.cb has "drq 0xf4 = 0xfc" for GPIO5)