Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41932 )
Change subject: northbridge/intel/broadwell: Add Kconfig ......................................................................
northbridge/intel/broadwell: Add Kconfig
Move the northbridge Kconfig settings to the corresponding scope. Also, correct `initialse` to `initialize`, as fixed on Haswell.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I40c86dd46532281a06759078c6ca87b4c4661b35 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/northbridge/intel/broadwell/Kconfig M src/northbridge/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/Kconfig 3 files changed, 121 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41932/1
diff --git a/src/northbridge/intel/broadwell/Kconfig b/src/northbridge/intel/broadwell/Kconfig new file mode 100644 index 0000000..3207a04 --- /dev/null +++ b/src/northbridge/intel/broadwell/Kconfig @@ -0,0 +1,119 @@ +config NORTHBRIDGE_INTEL_BROADWELL + def_bool n + select CACHE_MRC_SETTINGS + select CPU_INTEL_BROADWELL + select INTEL_GMA_ACPI + select MRC_SETTINGS_PROTECT + +if NORTHBRIDGE_INTEL_BROADWELL + +config BROADWELL_VBOOT_IN_BOOTBLOCK + depends on VBOOT + bool "Start verstage in bootblock" + default y + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Broadwell can either start verstage in a separate stage + right after the bootblock has run or it can start it + after romstage for compatibility reasons. + Broadwell however uses a mrc.bin to initialize memory which + needs to be located at a fixed offset. Therefore even with + a separate verstage starting after the bootblock that same + binary is used meaning a jump is made from RW to the RO region + and back to the RW region after the binary is done. + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config VGA_BIOS_ID + string + default "8086,0406" + +config DCACHE_RAM_BASE + hex + default 0xff7c0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE + must add up to a power of 2. + +config DCACHE_RAM_MRC_VAR_SIZE + hex + default 0x30000 + help + The amount of cache-as-ram region required by the reference code. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config HAVE_MRC + bool "Add a Memory Reference Code binary" + help + Select this option to add a Memory Reference Code binary to + the resulting coreboot image. + + Note: Without this binary coreboot will not work + +if HAVE_MRC + +config MRC_FILE + string "Intel Memory Reference Code path and filename" + depends on HAVE_MRC + default "mrc.bin" + help + The filename of the file to use as Memory Reference Code binary. + +config MRC_BIN_ADDRESS + hex + default 0xfffa0000 + +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + +endif # HAVE_MRC + +config PRE_GRAPHICS_DELAY + int "Graphics initialization delay in ms" + default 0 + help + On some systems, coreboot boots so fast that connected monitors + (mostly TVs) won't be able to wake up fast enough to talk to the + VBIOS. On those systems we need to wait for a bit before executing + the VBIOS. + +config HAVE_REFCODE_BLOB + depends on ARCH_X86 + bool "An external reference code blob should be put into cbfs." + default n + help + The reference code blob will be placed into cbfs. + +if HAVE_REFCODE_BLOB + +config REFCODE_BLOB_FILE + string "Path and filename to reference code blob." + default "refcode.elf" + help + The path and filename to the file to be added to cbfs. + +endif # HAVE_REFCODE_BLOB + +endif diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc index 77e96ce..cbcc631 100644 --- a/src/northbridge/intel/broadwell/Makefile.inc +++ b/src/northbridge/intel/broadwell/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_BROADWELL),y)
bootblock-y += bootblock.c
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2048d97..e61bee8 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -9,8 +9,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select BOOT_DEVICE_SUPPORTS_WRITES - select CACHE_MRC_SETTINGS - select CPU_INTEL_BROADWELL select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_SMI_HANDLER @@ -18,8 +16,7 @@ select HAVE_USBDEBUG select IOAPIC select INTEL_DESCRIPTOR_MODE_CAPABLE - select INTEL_GMA_ACPI - select MRC_SETTINGS_PROTECT + select NORTHBRIDGE_INTEL_BROADWELL select REG_SCRIPT select RTC select SOC_INTEL_COMMON @@ -52,98 +49,6 @@ bool default y
-config BROADWELL_VBOOT_IN_BOOTBLOCK - depends on VBOOT - bool "Start verstage in bootblock" - default y - select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE - help - Broadwell can either start verstage in a separate stage - right after the bootblock has run or it can start it - after romstage for compatibility reasons. - Broadwell however uses a mrc.bin to initialse memory which - needs to be located at a fixed offset. Therefore even with - a separate verstage starting after the bootblock that same - binary is used meaning a jump is made from RW to the RO region - and back to the RW region after the binary is done. - -config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK - -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - -config VGA_BIOS_ID - string - default "8086,0406" - -config DCACHE_RAM_BASE - hex - default 0xff7c0000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - help - The size of the cache-as-ram region required during bootblock - and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE - must add up to a power of 2. - -config DCACHE_RAM_MRC_VAR_SIZE - hex - default 0x30000 - help - The amount of cache-as-ram region required by the reference code. - -config DCACHE_BSP_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. - -config HAVE_MRC - bool "Add a Memory Reference Code binary" - help - Select this option to add a Memory Reference Code binary to - the resulting coreboot image. - - Note: Without this binary coreboot will not work - -if HAVE_MRC - -config MRC_FILE - string "Intel Memory Reference Code path and filename" - depends on HAVE_MRC - default "mrc.bin" - help - The filename of the file to use as Memory Reference Code binary. - -config MRC_BIN_ADDRESS - hex - default 0xfffa0000 - -# The UEFI System Agent binary needs to be at a fixed offset in the flash -# and can therefore only reside in the COREBOOT fmap region -config RO_REGION_ONLY - string - depends on VBOOT - default "mrc.bin" - -endif # HAVE_MRC - -config PRE_GRAPHICS_DELAY - int "Graphics initialization delay in ms" - default 0 - help - On some systems, coreboot boots so fast that connected monitors - (mostly TVs) won't be able to wake up fast enough to talk to the - VBIOS. On those systems we need to wait for a bit before executing - the VBIOS. - config INTEL_PCH_UART_CONSOLE bool "Use Serial IO UART for console" default n @@ -170,21 +75,4 @@ If you set this option to y, the serial IRQ machine will be operated in continuous mode.
-config HAVE_REFCODE_BLOB - depends on ARCH_X86 - bool "An external reference code blob should be put into cbfs." - default n - help - The reference code blob will be placed into cbfs. - -if HAVE_REFCODE_BLOB - -config REFCODE_BLOB_FILE - string "Path and filename to reference code blob." - default "refcode.elf" - help - The path and filename to the file to be added to cbfs. - -endif # HAVE_REFCODE_BLOB - endif
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41932
to look at the new patch set (#9).
Change subject: northbridge/intel/broadwell: Add Kconfig ......................................................................
northbridge/intel/broadwell: Add Kconfig
Move the northbridge Kconfig settings to the corresponding scope. Also, correct `initialse` to `initialize`, as fixed on Haswell.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I40c86dd46532281a06759078c6ca87b4c4661b35 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/northbridge/intel/broadwell/Kconfig M src/northbridge/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/Kconfig 3 files changed, 121 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41932/9
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41932
to look at the new patch set (#12).
Change subject: northbridge/intel/broadwell: Add Kconfig ......................................................................
northbridge/intel/broadwell: Add Kconfig
Move the northbridge Kconfig settings to the corresponding scope. Also, correct `initialse` to `initialize`, as fixed on Haswell.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I40c86dd46532281a06759078c6ca87b4c4661b35 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/northbridge/intel/broadwell/Kconfig M src/northbridge/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/Kconfig 3 files changed, 121 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41932/12
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41932 )
Change subject: northbridge/intel/broadwell: Add Kconfig ......................................................................
Abandoned
-
Angel Pons (Code Review)