[S] Change in coreboot[main]: soc/intel/pantherlake: Allow board-specific SOC memory config override

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87089?usp=email )

Change subject: soc/intel/pantherlake: Allow board-specific SOC memory config override
......................................................................

soc/intel/pantherlake: Allow board-specific SOC memory config override

This commit introduces a mechanism to allow mainboards to override
the default SOC memory initialization configuration for Panther Lake.

- Adds `variant_update_soc_memory_init_config` as a weak function
  in `variants.h` and `romstage.c` for board-specific implementations.
- Adds `mainboard_update_soc_memory_init_config` to `romstage.h`
  and its implementation in `romstage.c` calls the variant-specific
  weak function.
- In `fsp_params.c`, `platform_fsp_memory_init_params_cb` now calls
  `mainboard_update_soc_memory_init_config` to apply board-specific
  overrides to the SOC memory config before passing it to the FSP.

This enables finer-grained control over memory initialization parameters
at the variant level.

BUG=b:328770565
TEST=Able to reduce the boot time by 18ms.

Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/fatcat/romstage.c
M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
M src/soc/intel/pantherlake/include/soc/romstage.h
M src/soc/intel/pantherlake/romstage/fsp_params.c
4 files changed, 27 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/87089/1

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 7b56e28..90f443f 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -3,6 +3,7 @@
 #include <baseboard/variants.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
+#include <soc/soc_chip.h>
 #include <string.h>

/*
@@ -34,3 +35,15 @@

memcfg_init(memupd, mem_config, &spd_info, half_populated);
 }
+
+void __weak variant_update_soc_memory_init_config(
+	 struct soc_intel_pantherlake_config *config)
+{
+	/* default implementation does nothing */
+}
+
+void mainboard_update_soc_memory_init_config(
+	 struct soc_intel_pantherlake_config *config)
+{
+	variant_update_soc_memory_init_config(config);
+}
diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
index 2a70408..2c7f42d 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
@@ -23,6 +23,8 @@
 void variant_get_spd_info(struct mem_spd *spd_info);
 int variant_memory_sku(void);
 bool variant_is_half_populated(void);
+void variant_update_soc_memory_init_config(
+	 struct soc_intel_pantherlake_config *config);
 void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config);

enum s0ix_entry {
diff --git a/src/soc/intel/pantherlake/include/soc/romstage.h b/src/soc/intel/pantherlake/include/soc/romstage.h
index 733a11b..6864d12 100644
--- a/src/soc/intel/pantherlake/include/soc/romstage.h
+++ b/src/soc/intel/pantherlake/include/soc/romstage.h
@@ -6,6 +6,8 @@
 #include <fsp/api.h>
 #include <soc/soc_chip.h>

+void mainboard_update_soc_memory_init_config(
+	 struct soc_intel_pantherlake_config *config);
 void mainboard_memory_init_params(FSPM_UPD *memupd);
 void systemagent_early_init(void);

diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index b5fc93b..b2ebf8b 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -387,13 +387,22 @@
    ux_inform_user_of_update_operation("memory training", mupd);
 }

+__weak void mainboard_update_soc_memory_init_config(
+	 struct soc_intel_pantherlake_config *config)
+{
+	/* Override settings per board. */
+}
+
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	const struct soc_intel_pantherlake_config *config = config_of_soc();
+	struct soc_intel_pantherlake_config *config = (config_t *)config_of_soc();

if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER))
    	fill_fsp_event_handler(mupd);

+	/* Override settings per board if required. */
+	mainboard_update_soc_memory_init_config(config);
+
    soc_memory_init_params(&mupd->FspmConfig, config);

if (CONFIG(FSP_UGOP_EARLY_SIGN_OF_LIFE))