[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support

[Jérémy Compostella (Code Review)]

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Wonkyu Kim.

Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email )

Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
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Patch Set 17:

(8 comments)

Patchset:

PS16:
> why this CL is sitting on top of 3 other cls which seems related to FSP doing MP Init. […]

I agree. I cleaned-up the relation chain which should help smoothly land this patch faster.

File src/commonlib/include/commonlib/console/post_codes.h:

https://review.coreboot.org/c/coreboot/+/80275/comment/afc96322_fcf1adbf :
PS16, Line 337: MemoryInit
> why don't we use 0xa4 for FSP_M MultiPhase entry and 0xa5 for exit?

Done

File src/commonlib/include/commonlib/timestamp_serialized.h:

https://review.coreboot.org/c/coreboot/+/80275/comment/99337a3d_59e3c4c7 :
PS16, Line 143: 972
> why not 964 and 965 ?

Done

File src/drivers/intel/fsp2_0/include/fsp/info_header.h:

https://review.coreboot.org/c/coreboot/+/80275/comment/4da777fa_b56a3bbf :
PS16, Line 41: fsp_smm_init_entry_offset
> we don't need this, please mark reserved

Done

File src/drivers/intel/fsp2_0/include/fsp/util.h:

https://review.coreboot.org/c/coreboot/+/80275/comment/6e3540cc_e116af87 :
PS16, Line 83: };
             : 
             : struct fsp_multi_phase_get_number_of_phases_params {
             : 	uint32_t number_of_phases;
             : 	uint32_t phases_executed;
             : };
> nit: move after line #58 ?

Done

File src/drivers/intel/fsp2_0/memory_init.c:

https://review.coreboot.org/c/coreboot/+/80275/comment/d49225e2_c63535f4 :
PS16, Line 278: fspm_return_value_handler
> nit: why don't we create `fsp_return_value_handler` to address both FSP-M and S case now ?

There are fundamental differences between memory and silicon fsp return handler like multiphase ID or dependencies on GOP/VBT...

https://review.coreboot.org/c/coreboot/+/80275/comment/4fe4c0a3_c5a680e7 :
PS16, Line 433: 	fspm_multi_phase_init(hdr);
> should we avoid calling into fspm_multi_phase_init() if FSP version is not 2. […]

It would require guarding the function definition with `CONFIG_PLATFORM_USES_FSP2_4` and it will lead to the same result as the current implementation as the compiler optimized out that call.

File util/cbfstool/eventlog.c:

https://review.coreboot.org/c/coreboot/+/80275/comment/387dab7a_53cff450 :
PS16, Line 410: 		{POSTCODE_FSP_MULTI_PHASE_INIT_ENTRY, "FSP-M/S Multi Phase Init Enter"},
              : 		{POSTCODE_FSP_MULTI_PHASE_INIT_EXIT, "FPS-M/S Multi Phase Init Exit"},
> as suggested, keep different post codes

Done